Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66100655	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	67413259	1		T1	114455		T2	13061		T3	15115

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132369036	1		T1	229378		T2	26227		T3	30204
values[0x0]	543828	1		T1	28		T2	24		T3	23
values[0x1]	601050	1		T1	30		T2	15		T3	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52788361	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	80725553	1		T1	137211		T2	15739		T3	18205

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	369981	1		T1	885		T2	87		T3	145
valid_sources[0x01]	425678	1		T1	880		T2	86		T3	110
valid_sources[0x02]	371420	1		T1	857		T2	104		T3	127
valid_sources[0x03]	371449	1		T1	880		T2	102		T3	94
valid_sources[0x04]	373430	1		T1	892		T2	103		T3	119
valid_sources[0x05]	374019	1		T1	905		T2	103		T3	117
valid_sources[0x06]	387686	1		T1	866		T2	93		T3	110
valid_sources[0x07]	370641	1		T1	957		T2	105		T3	117
valid_sources[0x08]	736231	1		T1	914		T2	99		T3	140
valid_sources[0x09]	384481	1		T1	867		T2	121		T3	119
valid_sources[0x0a]	370234	1		T1	861		T2	91		T3	112
valid_sources[0x0b]	369487	1		T1	955		T2	111		T3	109
valid_sources[0x0c]	370160	1		T1	914		T2	100		T3	128
valid_sources[0x0d]	689373	1		T1	901		T2	102		T3	100
valid_sources[0x0e]	1706945	1		T1	905		T2	116		T3	115
valid_sources[0x0f]	368203	1		T1	875		T2	106		T3	119
valid_sources[0x10]	371099	1		T1	929		T2	93		T3	118
valid_sources[0x11]	384440	1		T1	866		T2	82		T3	130
valid_sources[0x12]	434979	1		T1	894		T2	107		T3	127
valid_sources[0x13]	369181	1		T1	851		T2	118		T3	119
valid_sources[0x14]	371627	1		T1	901		T2	91		T3	127
valid_sources[0x15]	371391	1		T1	922		T2	88		T3	113
valid_sources[0x16]	371036	1		T1	969		T2	105		T3	139
valid_sources[0x17]	374678	1		T1	884		T2	93		T3	86
valid_sources[0x18]	368677	1		T1	910		T2	96		T3	137
valid_sources[0x19]	373259	1		T1	896		T2	81		T3	116
valid_sources[0x1a]	368254	1		T1	957		T2	101		T3	144
valid_sources[0x1b]	397887	1		T1	920		T2	101		T3	136
valid_sources[0x1c]	378770	1		T1	871		T2	93		T3	103
valid_sources[0x1d]	371178	1		T1	966		T2	100		T3	117
valid_sources[0x1e]	372991	1		T1	884		T2	99		T3	109
valid_sources[0x1f]	368880	1		T1	850		T2	101		T3	115
valid_sources[0x20]	368642	1		T1	881		T2	117		T3	94
valid_sources[0x21]	558070	1		T1	896		T2	107		T3	118
valid_sources[0x22]	922310	1		T1	905		T2	107		T3	114
valid_sources[0x23]	369882	1		T1	990		T2	108		T3	114
valid_sources[0x24]	429602	1		T1	899		T2	91		T3	93
valid_sources[0x25]	410096	1		T1	836		T2	114		T3	107
valid_sources[0x26]	401246	1		T1	891		T2	121		T3	101
valid_sources[0x27]	1362773	1		T1	916		T2	97		T3	110
valid_sources[0x28]	629857	1		T1	886		T2	102		T3	114
valid_sources[0x29]	369554	1		T1	912		T2	112		T3	116
valid_sources[0x2a]	369148	1		T1	901		T2	117		T3	115
valid_sources[0x2b]	369859	1		T1	879		T2	91		T3	120
valid_sources[0x2c]	371060	1		T1	901		T2	96		T3	102
valid_sources[0x2d]	1689826	1		T1	893		T2	95		T3	133
valid_sources[0x2e]	369154	1		T1	887		T2	111		T3	122
valid_sources[0x2f]	371127	1		T1	945		T2	102		T3	118
valid_sources[0x30]	702271	1		T1	932		T2	106		T3	119
valid_sources[0x31]	674211	1		T1	926		T2	100		T3	109
valid_sources[0x32]	374380	1		T1	916		T2	110		T3	114
valid_sources[0x33]	371741	1		T1	863		T2	106		T3	123
valid_sources[0x34]	370347	1		T1	861		T2	111		T3	102
valid_sources[0x35]	371141	1		T1	924		T2	104		T3	116
valid_sources[0x36]	729333	1		T1	864		T2	98		T3	124
valid_sources[0x37]	368947	1		T1	854		T2	103		T3	128
valid_sources[0x38]	372699	1		T1	912		T2	115		T3	122
valid_sources[0x39]	372738	1		T1	862		T2	103		T3	119
valid_sources[0x3a]	427178	1		T1	939		T2	91		T3	129
valid_sources[0x3b]	594681	1		T1	900		T2	108		T3	138
valid_sources[0x3c]	370628	1		T1	875		T2	120		T3	137
valid_sources[0x3d]	372988	1		T1	954		T2	102		T3	111
valid_sources[0x3e]	369945	1		T1	943		T2	113		T3	108
valid_sources[0x3f]	369403	1		T1	916		T2	131		T3	122
valid_sources[0x40]	371060	1		T1	944		T2	125		T3	139
valid_sources[0x41]	387183	1		T1	901		T2	91		T3	104
valid_sources[0x42]	369320	1		T1	842		T2	101		T3	111
valid_sources[0x43]	373144	1		T1	922		T2	100		T3	126
valid_sources[0x44]	427209	1		T1	885		T2	98		T3	120
valid_sources[0x45]	1009564	1		T1	889		T2	93		T3	104
valid_sources[0x46]	369270	1		T1	868		T2	94		T3	129
valid_sources[0x47]	369701	1		T1	805		T2	98		T3	114
valid_sources[0x48]	378538	1		T1	907		T2	117		T3	112
valid_sources[0x49]	1486380	1		T1	837		T2	112		T3	130
valid_sources[0x4a]	370397	1		T1	894		T2	113		T3	130
valid_sources[0x4b]	369778	1		T1	870		T2	92		T3	128
valid_sources[0x4c]	370596	1		T1	883		T2	86		T3	134
valid_sources[0x4d]	369999	1		T1	833		T2	98		T3	108
valid_sources[0x4e]	370960	1		T1	915		T2	90		T3	122
valid_sources[0x4f]	2328474	1		T1	964		T2	76		T3	130
valid_sources[0x50]	368587	1		T1	888		T2	106		T3	128
valid_sources[0x51]	371918	1		T1	885		T2	86		T3	139
valid_sources[0x52]	375225	1		T1	898		T2	81		T3	86
valid_sources[0x53]	371925	1		T1	872		T2	100		T3	101
valid_sources[0x54]	367783	1		T1	919		T2	97		T3	111
valid_sources[0x55]	371787	1		T1	905		T2	105		T3	120
valid_sources[0x56]	370108	1		T1	881		T2	99		T3	99
valid_sources[0x57]	369526	1		T1	863		T2	85		T3	128
valid_sources[0x58]	371738	1		T1	904		T2	105		T3	105
valid_sources[0x59]	367247	1		T1	885		T2	94		T3	100
valid_sources[0x5a]	372061	1		T1	880		T2	109		T3	124
valid_sources[0x5b]	419563	1		T1	852		T2	113		T3	111
valid_sources[0x5c]	369295	1		T1	901		T2	116		T3	114
valid_sources[0x5d]	371632	1		T1	898		T2	89		T3	150
valid_sources[0x5e]	371985	1		T1	912		T2	82		T3	94
valid_sources[0x5f]	416149	1		T1	877		T2	94		T3	118
valid_sources[0x60]	370584	1		T1	900		T2	118		T3	136
valid_sources[0x61]	370734	1		T1	922		T2	100		T3	112
valid_sources[0x62]	439406	1		T1	886		T2	117		T3	126
valid_sources[0x63]	368766	1		T1	894		T2	87		T3	116
valid_sources[0x64]	371573	1		T1	935		T2	105		T3	139
valid_sources[0x65]	369681	1		T1	859		T2	79		T3	123
valid_sources[0x66]	1155584	1		T1	832		T2	107		T3	99
valid_sources[0x67]	455032	1		T1	900		T2	101		T3	106
valid_sources[0x68]	368709	1		T1	871		T2	107		T3	123
valid_sources[0x69]	369197	1		T1	852		T2	107		T3	127
valid_sources[0x6a]	370174	1		T1	896		T2	119		T3	149
valid_sources[0x6b]	962629	1		T1	898		T2	87		T3	134
valid_sources[0x6c]	729838	1		T1	883		T2	115		T3	121
valid_sources[0x6d]	368395	1		T1	915		T2	101		T3	123
valid_sources[0x6e]	491991	1		T1	874		T2	101		T3	114
valid_sources[0x6f]	368945	1		T1	852		T2	100		T3	92
valid_sources[0x70]	371483	1		T1	933		T2	107		T3	118
valid_sources[0x71]	369924	1		T1	850		T2	105		T3	131
valid_sources[0x72]	372073	1		T1	897		T2	97		T3	127
valid_sources[0x73]	443197	1		T1	892		T2	93		T3	126
valid_sources[0x74]	385220	1		T1	918		T2	111		T3	119
valid_sources[0x75]	1095972	1		T1	892		T2	96		T3	128
valid_sources[0x76]	368485	1		T1	909		T2	117		T3	135
valid_sources[0x77]	371092	1		T1	918		T2	106		T3	138
valid_sources[0x78]	372232	1		T1	924		T2	96		T3	144
valid_sources[0x79]	435936	1		T1	894		T2	92		T3	123
valid_sources[0x7a]	370514	1		T1	860		T2	93		T3	111
valid_sources[0x7b]	371513	1		T1	913		T2	92		T3	110
valid_sources[0x7c]	372458	1		T1	928		T2	124		T3	95
valid_sources[0x7d]	367976	1		T1	908		T2	115		T3	116
valid_sources[0x7e]	368337	1		T1	898		T2	105		T3	124
valid_sources[0x7f]	370240	1		T1	884		T2	102		T3	118
valid_sources[0x80]	407306	1		T1	872		T2	129		T3	118

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66347006

1

T1

114413

T2

13032

T3

15096

values[0x0]

all_enables

biggest_size

533169

1

T1

18

T2

19

T3

11

values[0x1]

all_enables

biggest_size

533084

1

T1

24

T2

10

T3

8