Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1846172	0	0
cfg0_rd_A	2147483647	6465	0	0
compare_lower0_0_rd_A	2147483647	7171	0	0
compare_upper0_0_rd_A	2147483647	6624	0	0
ctrl_rd_A	2147483647	6061	0	0
intr_enable0_rd_A	2147483647	7656	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1846172	0	0
T12	683515	198123	0	0
T13	702546	172076	0	0
T14	0	129015	0	0
T37	0	264452	0	0
T38	0	175873	0	0
T39	0	80464	0	0
T40	0	161953	0	0
T41	0	86702	0	0
T42	0	48235	0	0
T43	0	44020	0	0
T44	405216	0	0	0
T45	602451	0	0	0
T46	834788	0	0	0
T47	107918	0	0	0
T48	161028	0	0	0
T49	127970	0	0	0
T50	555243	0	0	0
T51	867005	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6465	0	0
T12	683515	1196	0	0
T13	702546	873	0	0
T33	0	9	0	0
T34	0	36	0	0
T37	0	2590	0	0
T44	405216	0	0	0
T45	602451	0	0	0
T46	834788	0	0	0
T47	107918	0	0	0
T48	161028	0	0	0
T49	127970	0	0	0
T50	555243	0	0	0
T51	867005	0	0	0
T52	0	276	0	0
T53	0	5	0	0
T54	0	1	0	0
T55	0	10	0	0
T56	0	85	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7171	0	0
T12	683515	1283	0	0
T13	702546	994	0	0
T33	0	44	0	0
T34	0	31	0	0
T37	0	3022	0	0
T44	405216	0	0	0
T45	602451	0	0	0
T46	834788	0	0	0
T47	107918	0	0	0
T48	161028	0	0	0
T49	127970	0	0	0
T50	555243	0	0	0
T51	867005	0	0	0
T52	0	452	0	0
T53	0	4	0	0
T55	0	12	0	0
T56	0	78	0	0
T57	0	4	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6624	0	0
T12	683515	1105	0	0
T13	702546	1050	0	0
T33	0	31	0	0
T34	0	10	0	0
T37	0	2790	0	0
T44	405216	0	0	0
T45	602451	0	0	0
T46	834788	0	0	0
T47	107918	0	0	0
T48	161028	0	0	0
T49	127970	0	0	0
T50	555243	0	0	0
T51	867005	0	0	0
T52	0	415	0	0
T53	0	5	0	0
T54	0	5	0	0
T56	0	87	0	0
T57	0	16	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6061	0	0
T12	683515	1068	0	0
T13	702546	1002	0	0
T33	0	44	0	0
T34	0	26	0	0
T37	0	2254	0	0
T44	405216	0	0	0
T45	602451	0	0	0
T46	834788	0	0	0
T47	107918	0	0	0
T48	161028	0	0	0
T49	127970	0	0	0
T50	555243	0	0	0
T51	867005	0	0	0
T52	0	327	0	0
T53	0	4	0	0
T55	0	23	0	0
T56	0	74	0	0
T57	0	10	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7656	0	0
T12	0	1159	0	0
T13	0	925	0	0
T15	5435	0	0	0
T20	27661	0	0	0
T21	729028	35	0	0
T22	157248	0	0	0
T23	259218	0	0	0
T24	568107	0	0	0
T25	155434	0	0	0
T36	256142	24	0	0
T37	0	3138	0	0
T45	0	62	0	0
T58	0	38	0	0
T59	0	30	0	0
T60	0	10	0	0
T61	0	72	0	0
T62	105125	0	0	0
T63	222277	0	0	0