Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1667640	0	0
cfg0_rd_A	2147483647	6551	0	0
compare_lower0_0_rd_A	2147483647	6602	0	0
compare_upper0_0_rd_A	2147483647	6455	0	0
ctrl_rd_A	2147483647	6290	0	0
intr_enable0_rd_A	2147483647	8215	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1667640	0	0
T4	216775	89178	0	0
T5	690381	0	0	0
T6	600815	0	0	0
T7	466459	0	0	0
T8	238402	0	0	0
T9	148530	0	0	0
T10	342612	0	0	0
T11	0	209986	0	0
T12	0	88176	0	0
T27	124847	0	0	0
T34	0	232979	0	0
T35	0	162404	0	0
T36	0	122166	0	0
T37	0	15602	0	0
T38	0	19857	0	0
T39	0	220791	0	0
T40	0	6560	0	0
T41	621644	0	0	0
T42	931357	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6551	0	0
T28	0	186	0	0
T30	0	20	0	0
T36	461249	1221	0	0
T37	109263	175	0	0
T43	0	1600	0	0
T44	0	1472	0	0
T45	0	4	0	0
T46	0	444	0	0
T47	0	71	0	0
T48	0	13	0	0
T49	131474	0	0	0
T50	412283	0	0	0
T51	874231	0	0	0
T52	142026	0	0	0
T53	813714	0	0	0
T54	17105	0	0	0
T55	421457	0	0	0
T56	432851	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6602	0	0
T28	0	104	0	0
T30	0	7	0	0
T36	461249	1421	0	0
T37	109263	182	0	0
T43	0	1809	0	0
T44	0	1358	0	0
T46	0	432	0	0
T47	0	30	0	0
T48	0	26	0	0
T49	131474	0	0	0
T50	412283	0	0	0
T51	874231	0	0	0
T52	142026	0	0	0
T53	813714	0	0	0
T54	17105	0	0	0
T55	421457	0	0	0
T56	432851	0	0	0
T57	0	4	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6455	0	0
T28	0	148	0	0
T30	0	32	0	0
T36	461249	1353	0	0
T37	109263	157	0	0
T43	0	1754	0	0
T44	0	1193	0	0
T45	0	4	0	0
T46	0	384	0	0
T47	0	46	0	0
T48	0	13	0	0
T49	131474	0	0	0
T50	412283	0	0	0
T51	874231	0	0	0
T52	142026	0	0	0
T53	813714	0	0	0
T54	17105	0	0	0
T55	421457	0	0	0
T56	432851	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6290	0	0
T28	0	104	0	0
T30	0	37	0	0
T36	461249	1255	0	0
T37	109263	237	0	0
T43	0	1592	0	0
T44	0	1233	0	0
T45	0	1	0	0
T46	0	399	0	0
T47	0	45	0	0
T48	0	19	0	0
T49	131474	0	0	0
T50	412283	0	0	0
T51	874231	0	0	0
T52	142026	0	0	0
T53	813714	0	0	0
T54	17105	0	0	0
T55	421457	0	0	0
T56	432851	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8215	0	0
T11	537135	0	0	0
T27	124847	20	0	0
T36	0	1579	0	0
T37	0	246	0	0
T41	621644	0	0	0
T42	931357	0	0	0
T58	0	4	0	0
T59	0	85	0	0
T60	0	54	0	0
T61	0	36	0	0
T62	0	38	0	0
T63	0	51	0	0
T64	0	54	0	0
T65	1864	0	0	0
T66	717145	0	0	0
T67	652568	0	0	0
T68	918296	0	0	0
T69	146733	0	0	0
T70	238775	0	0	0