Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1276711	0	0
cfg0_rd_A	2147483647	6204	0	0
compare_lower0_0_rd_A	2147483647	6643	0	0
compare_upper0_0_rd_A	2147483647	5897	0	0
ctrl_rd_A	2147483647	5809	0	0
intr_enable0_rd_A	2147483647	7631	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1276711	0	0
T12	329195	82090	0	0
T13	0	133991	0	0
T14	0	111552	0	0
T29	0	13	0	0
T35	0	139160	0	0
T36	0	32040	0	0
T37	0	132381	0	0
T38	0	85205	0	0
T39	0	234893	0	0
T40	0	310371	0	0
T41	233447	0	0	0
T42	277346	0	0	0
T43	1672	0	0	0
T44	334078	0	0	0
T45	158761	0	0	0
T46	103026	0	0	0
T47	130395	0	0	0
T48	529103	0	0	0
T49	831498	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6204	0	0
T12	329195	405	0	0
T32	0	74	0	0
T35	0	1421	0	0
T38	0	926	0	0
T39	0	2267	0	0
T41	233447	0	0	0
T42	277346	0	0	0
T43	1672	0	0	0
T44	334078	0	0	0
T45	158761	0	0	0
T46	103026	0	0	0
T47	130395	0	0	0
T48	529103	0	0	0
T49	831498	0	0	0
T50	0	16	0	0
T51	0	11	0	0
T52	0	15	0	0
T53	0	19	0	0
T54	0	9	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6643	0	0
T12	329195	414	0	0
T32	0	67	0	0
T35	0	1505	0	0
T38	0	955	0	0
T39	0	2701	0	0
T41	233447	0	0	0
T42	277346	0	0	0
T43	1672	0	0	0
T44	334078	0	0	0
T45	158761	0	0	0
T46	103026	0	0	0
T47	130395	0	0	0
T48	529103	0	0	0
T49	831498	0	0	0
T50	0	19	0	0
T51	0	21	0	0
T52	0	9	0	0
T53	0	20	0	0
T54	0	6	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5897	0	0
T12	329195	448	0	0
T32	0	60	0	0
T35	0	1392	0	0
T38	0	815	0	0
T39	0	2229	0	0
T41	233447	0	0	0
T42	277346	0	0	0
T43	1672	0	0	0
T44	334078	0	0	0
T45	158761	0	0	0
T46	103026	0	0	0
T47	130395	0	0	0
T48	529103	0	0	0
T49	831498	0	0	0
T50	0	23	0	0
T51	0	18	0	0
T53	0	18	0	0
T54	0	11	0	0
T55	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5809	0	0
T12	329195	412	0	0
T32	0	52	0	0
T35	0	1199	0	0
T38	0	874	0	0
T39	0	2257	0	0
T41	233447	0	0	0
T42	277346	0	0	0
T43	1672	0	0	0
T44	334078	0	0	0
T45	158761	0	0	0
T46	103026	0	0	0
T47	130395	0	0	0
T48	529103	0	0	0
T49	831498	0	0	0
T50	0	9	0	0
T51	0	15	0	0
T52	0	9	0	0
T53	0	10	0	0
T54	0	16	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7631	0	0
T3	1768	5	0	0
T4	212261	0	0	0
T5	68374	0	0	0
T6	770133	0	0	0
T7	190606	0	0	0
T8	303558	0	0	0
T9	379813	0	0	0
T10	4975	0	0	0
T11	158524	49	0	0
T12	0	472	0	0
T23	0	44	0	0
T25	0	7	0	0
T35	0	1462	0	0
T56	0	42	0	0
T57	0	106	0	0
T58	0	26	0	0
T59	0	39	0	0
T60	317001	0	0	0