Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61544105	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	63133209	1		T1	109165		T2	817393		T3	4380

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	123306225	1		T1	217746		T2	163337		T3	8788
values[0x0]	651451	1		T1	34		T2	13		T3	11
values[0x1]	719638	1		T1	26		T2	16		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49143977	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	75533337	1		T1	131037		T2	981210		T3	5262

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	364438	1		T2	6321		T3	35		T5	60
valid_sources[0x01]	416304	1		T2	6345		T3	43		T5	40
valid_sources[0x02]	366981	1		T2	6295		T3	22		T5	53
valid_sources[0x03]	366618	1		T2	6355		T3	26		T5	52
valid_sources[0x04]	368050	1		T2	6971		T3	23		T5	43
valid_sources[0x05]	368208	1		T2	6244		T3	46		T5	60
valid_sources[0x06]	365141	1		T2	5417		T3	29		T5	52
valid_sources[0x07]	363499	1		T2	7079		T3	32		T5	43
valid_sources[0x08]	369454	1		T2	6061		T3	23		T5	35
valid_sources[0x09]	364194	1		T2	6023		T3	41		T5	49
valid_sources[0x0a]	365897	1		T2	6258		T3	41		T5	44
valid_sources[0x0b]	3494120	1		T2	6802		T3	43		T5	69
valid_sources[0x0c]	695943	1		T2	6226		T3	18		T5	49
valid_sources[0x0d]	363513	1		T2	7653		T3	16		T5	58
valid_sources[0x0e]	366188	1		T2	5648		T3	27		T5	58
valid_sources[0x0f]	384605	1		T2	6845		T3	34		T5	65
valid_sources[0x10]	365754	1		T2	6649		T3	44		T5	52
valid_sources[0x11]	1447030	1		T2	5677		T3	31		T5	50
valid_sources[0x12]	731995	1		T2	6607		T3	46		T5	56
valid_sources[0x13]	572808	1		T2	6909		T3	31		T5	66
valid_sources[0x14]	366465	1		T2	5644		T3	33		T5	55
valid_sources[0x15]	367189	1		T2	5865		T3	30		T5	60
valid_sources[0x16]	367446	1		T2	6315		T3	15		T5	54
valid_sources[0x17]	367548	1		T2	5782		T3	25		T5	70
valid_sources[0x18]	367416	1		T2	7114		T3	25		T5	55
valid_sources[0x19]	366197	1		T2	5407		T3	34		T5	51
valid_sources[0x1a]	362919	1		T2	5966		T3	42		T5	56
valid_sources[0x1b]	363645	1		T2	5884		T3	34		T5	55
valid_sources[0x1c]	368223	1		T2	6931		T3	47		T5	67
valid_sources[0x1d]	1013301	1		T2	5988		T3	36		T5	71
valid_sources[0x1e]	363050	1		T2	5688		T3	34		T5	47
valid_sources[0x1f]	367089	1		T2	6399		T3	30		T5	63
valid_sources[0x20]	558204	1		T2	5828		T3	22		T5	51
valid_sources[0x21]	377005	1		T2	5990		T3	34		T5	50
valid_sources[0x22]	369090	1		T2	6437		T3	24		T5	59
valid_sources[0x23]	366317	1		T2	7138		T3	33		T5	59
valid_sources[0x24]	367115	1		T2	6373		T3	24		T5	49
valid_sources[0x25]	365420	1		T2	6755		T3	37		T5	53
valid_sources[0x26]	364682	1		T2	6072		T3	21		T5	49
valid_sources[0x27]	364081	1		T2	6397		T3	32		T5	50
valid_sources[0x28]	1850457	1		T2	6016		T3	26		T5	53
valid_sources[0x29]	362718	1		T2	6277		T3	49		T5	58
valid_sources[0x2a]	365078	1		T2	6133		T3	49		T5	48
valid_sources[0x2b]	363707	1		T2	6508		T3	33		T5	54
valid_sources[0x2c]	367245	1		T2	6793		T3	34		T5	50
valid_sources[0x2d]	365100	1		T2	5675		T3	33		T5	53
valid_sources[0x2e]	363289	1		T2	6114		T3	32		T5	32
valid_sources[0x2f]	387721	1		T2	6491		T3	31		T5	62
valid_sources[0x30]	365523	1		T2	6865		T3	48		T5	47
valid_sources[0x31]	365805	1		T2	5915		T3	31		T5	46
valid_sources[0x32]	366734	1		T2	6228		T3	37		T5	51
valid_sources[0x33]	582967	1		T2	6927		T3	28		T5	50
valid_sources[0x34]	366906	1		T2	5937		T3	34		T5	58
valid_sources[0x35]	371615	1		T2	6285		T3	32		T5	48
valid_sources[0x36]	368393	1		T2	6706		T3	37		T5	45
valid_sources[0x37]	365822	1		T2	7167		T3	32		T5	50
valid_sources[0x38]	368671	1		T2	6124		T3	27		T5	48
valid_sources[0x39]	366009	1		T2	6793		T3	33		T5	56
valid_sources[0x3a]	367555	1		T2	5947		T3	32		T5	54
valid_sources[0x3b]	364144	1		T2	6621		T3	26		T5	72
valid_sources[0x3c]	366819	1		T2	6057		T3	27		T5	55
valid_sources[0x3d]	365221	1		T2	7112		T3	38		T5	50
valid_sources[0x3e]	365668	1		T2	5701		T3	28		T5	52
valid_sources[0x3f]	366035	1		T2	6051		T3	27		T5	59
valid_sources[0x40]	364891	1		T2	6470		T3	34		T5	43
valid_sources[0x41]	366990	1		T2	6654		T3	40		T5	58
valid_sources[0x42]	361840	1		T2	5627		T3	48		T5	51
valid_sources[0x43]	381063	1		T2	6942		T3	32		T5	59
valid_sources[0x44]	366594	1		T2	6891		T3	38		T5	58
valid_sources[0x45]	367208	1		T2	6206		T3	46		T5	37
valid_sources[0x46]	670196	1		T2	6303		T3	35		T5	57
valid_sources[0x47]	363639	1		T2	6297		T3	26		T5	46
valid_sources[0x48]	807405	1		T2	6430		T3	8		T5	48
valid_sources[0x49]	366969	1		T2	6778		T3	41		T5	59
valid_sources[0x4a]	378595	1		T2	6625		T3	36		T5	52
valid_sources[0x4b]	1414902	1		T2	6920		T3	49		T5	37
valid_sources[0x4c]	372329	1		T2	5908		T3	40		T5	48
valid_sources[0x4d]	371789	1		T2	5714		T3	34		T5	51
valid_sources[0x4e]	366089	1		T2	6573		T3	36		T5	36
valid_sources[0x4f]	365758	1		T2	6351		T3	36		T5	52
valid_sources[0x50]	366124	1		T2	6123		T3	30		T5	56
valid_sources[0x51]	366608	1		T2	7069		T3	30		T5	58
valid_sources[0x52]	381280	1		T2	6515		T3	34		T5	55
valid_sources[0x53]	3097859	1		T2	5347		T3	28		T5	51
valid_sources[0x54]	363420	1		T2	6028		T3	40		T5	50
valid_sources[0x55]	367090	1		T2	7259		T3	33		T5	41
valid_sources[0x56]	366738	1		T2	6907		T3	34		T5	67
valid_sources[0x57]	365874	1		T2	7045		T3	23		T5	53
valid_sources[0x58]	363361	1		T2	6394		T3	25		T5	48
valid_sources[0x59]	365937	1		T2	6901		T3	35		T5	48
valid_sources[0x5a]	366927	1		T2	6887		T3	25		T5	57
valid_sources[0x5b]	368383	1		T2	6808		T3	34		T5	73
valid_sources[0x5c]	364450	1		T2	6518		T3	44		T5	48
valid_sources[0x5d]	366545	1		T2	6395		T3	53		T5	51
valid_sources[0x5e]	364148	1		T2	6078		T3	35		T5	55
valid_sources[0x5f]	364832	1		T2	6029		T3	25		T5	52
valid_sources[0x60]	477078	1		T2	5589		T3	36		T5	51
valid_sources[0x61]	364151	1		T2	6423		T3	39		T5	65
valid_sources[0x62]	366111	1		T2	5810		T3	35		T5	42
valid_sources[0x63]	362241	1		T2	6339		T3	43		T5	47
valid_sources[0x64]	367714	1		T2	6821		T3	51		T5	52
valid_sources[0x65]	365431	1		T2	6136		T3	39		T5	46
valid_sources[0x66]	418859	1		T2	6945		T3	33		T5	65
valid_sources[0x67]	408336	1		T2	5591		T3	53		T5	59
valid_sources[0x68]	812130	1		T2	6255		T3	39		T5	34
valid_sources[0x69]	368238	1		T2	6692		T3	50		T5	59
valid_sources[0x6a]	366600	1		T2	6505		T3	35		T5	59
valid_sources[0x6b]	369882	1		T2	6163		T3	70		T5	60
valid_sources[0x6c]	365067	1		T2	7108		T3	34		T5	64
valid_sources[0x6d]	364979	1		T2	6821		T3	20		T5	36
valid_sources[0x6e]	368374	1		T2	6998		T3	51		T5	65
valid_sources[0x6f]	420146	1		T2	7036		T3	37		T5	65
valid_sources[0x70]	369058	1		T2	6896		T3	30		T5	50
valid_sources[0x71]	365919	1		T2	7361		T3	29		T5	43
valid_sources[0x72]	367559	1		T2	6399		T3	33		T5	63
valid_sources[0x73]	366831	1		T2	6153		T3	50		T5	54
valid_sources[0x74]	399477	1		T2	5936		T3	51		T5	66
valid_sources[0x75]	366335	1		T2	6942		T3	25		T5	61
valid_sources[0x76]	366885	1		T2	6203		T3	19		T5	53
valid_sources[0x77]	796091	1		T2	6116		T3	38		T5	51
valid_sources[0x78]	472486	1		T2	6015		T3	28		T5	51
valid_sources[0x79]	363938	1		T2	5602		T3	36		T5	58
valid_sources[0x7a]	516705	1		T2	6390		T3	32		T5	61
valid_sources[0x7b]	2382980	1		T2	6110		T3	36		T5	51
valid_sources[0x7c]	364842	1		T2	6597		T3	25		T5	64
valid_sources[0x7d]	1095362	1		T2	6308		T3	42		T5	44
valid_sources[0x7e]	369822	1		T2	6314		T3	42		T5	58
valid_sources[0x7f]	366710	1		T2	6746		T3	27		T5	65
valid_sources[0x80]	390490	1		T2	5842		T3	21		T5	50

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61855363

1

T1

109119

T2

817377

T3

4353

values[0x0]

all_enables

biggest_size

639504

1

T1

29

T2

7

T3

9

values[0x1]

all_enables

biggest_size

638342

1

T1

17

T2

9

T3

18