Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2229856	0	0
cfg0_rd_A	2147483647	4552	0	0
compare_lower0_0_rd_A	2147483647	5007	0	0
compare_upper0_0_rd_A	2147483647	4801	0	0
ctrl_rd_A	2147483647	4600	0	0
intr_enable0_rd_A	2147483647	6164	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2229856	0	0
T13	306478	94335	0	0
T14	808779	206977	0	0
T15	0	194406	0	0
T27	111114	0	0	0
T28	568155	0	0	0
T38	0	33163	0	0
T39	0	353615	0	0
T40	0	135476	0	0
T41	0	300806	0	0
T42	0	103854	0	0
T43	0	597021	0	0
T44	0	36499	0	0
T45	604789	0	0	0
T46	172578	0	0	0
T47	143898	0	0	0
T48	186474	0	0	0
T49	107107	0	0	0
T50	625945	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4552	0	0
T14	808779	1954	0	0
T31	0	177	0	0
T35	0	404	0	0
T38	0	387	0	0
T50	625945	0	0	0
T51	0	813	0	0
T52	0	13	0	0
T53	0	17	0	0
T54	0	49	0	0
T55	0	10	0	0
T56	0	14	0	0
T57	131459	0	0	0
T58	272792	0	0	0
T59	281832	0	0	0
T60	115267	0	0	0
T61	230786	0	0	0
T62	984746	0	0	0
T63	142330	0	0	0
T64	195493	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5007	0	0
T14	808779	2406	0	0
T31	0	107	0	0
T35	0	441	0	0
T38	0	348	0	0
T50	625945	0	0	0
T51	0	916	0	0
T52	0	11	0	0
T53	0	30	0	0
T54	0	44	0	0
T55	0	4	0	0
T57	131459	0	0	0
T58	272792	0	0	0
T59	281832	0	0	0
T60	115267	0	0	0
T61	230786	0	0	0
T62	984746	0	0	0
T63	142330	0	0	0
T64	195493	0	0	0
T65	0	3	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4801	0	0
T14	808779	2138	0	0
T31	0	122	0	0
T35	0	425	0	0
T38	0	374	0	0
T50	625945	0	0	0
T51	0	881	0	0
T52	0	7	0	0
T53	0	43	0	0
T54	0	108	0	0
T55	0	11	0	0
T57	131459	0	0	0
T58	272792	0	0	0
T59	281832	0	0	0
T60	115267	0	0	0
T61	230786	0	0	0
T62	984746	0	0	0
T63	142330	0	0	0
T64	195493	0	0	0
T65	0	9	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4600	0	0
T14	808779	2154	0	0
T31	0	114	0	0
T35	0	402	0	0
T38	0	285	0	0
T50	625945	0	0	0
T51	0	892	0	0
T52	0	10	0	0
T53	0	12	0	0
T54	0	29	0	0
T55	0	9	0	0
T57	131459	0	0	0
T58	272792	0	0	0
T59	281832	0	0	0
T60	115267	0	0	0
T61	230786	0	0	0
T62	984746	0	0	0
T63	142330	0	0	0
T64	195493	0	0	0
T65	0	5	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6164	0	0
T12	228809	0	0	0
T14	0	2387	0	0
T32	128777	15	0	0
T33	493231	0	0	0
T38	0	432	0	0
T66	0	9	0	0
T67	0	64	0	0
T68	0	38	0	0
T69	0	49	0	0
T70	0	51	0	0
T71	0	12	0	0
T72	0	54	0	0
T73	831757	0	0	0
T74	492932	0	0	0
T75	807950	0	0	0
T76	141024	0	0	0
T77	135615	0	0	0
T78	173663	0	0	0
T79	112938	0	0	0