Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1007690	0	0
cfg0_rd_A	2147483647	813	0	0
compare_lower0_0_rd_A	2147483647	650	0	0
compare_upper0_0_rd_A	2147483647	641	0	0
ctrl_rd_A	2147483647	694	0	0
intr_enable0_rd_A	2147483647	1343	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1007690	0	0
T12	210011	87447	0	0
T13	0	180624	0	0
T14	0	208721	0	0
T29	0	16	0	0
T35	0	140491	0	0
T36	0	272438	0	0
T37	0	20779	0	0
T38	0	84304	0	0
T39	0	179	0	0
T40	0	110	0	0
T41	918559	0	0	0
T42	124574	0	0	0
T43	147109	0	0	0
T44	880213	0	0	0
T45	142724	0	0	0
T46	137532	0	0	0
T47	142874	0	0	0
T48	421268	0	0	0
T49	113102	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	813	0	0
T31	7434	109	0	0
T50	1657	4	0	0
T51	2920	61	0	0
T52	2471	4	0	0
T53	3535	16	0	0
T54	1938	3	0	0
T55	1514	5	0	0
T56	2844	30	0	0
T57	7221	5	0	0
T58	1811	7	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	650	0	0
T31	7434	65	0	0
T50	1657	5	0	0
T51	2920	37	0	0
T52	2471	7	0	0
T53	3535	15	0	0
T54	1938	13	0	0
T55	1514	6	0	0
T56	2844	32	0	0
T57	7221	1	0	0
T58	1811	12	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	641	0	0
T31	7434	89	0	0
T50	1657	6	0	0
T51	2920	59	0	0
T52	2471	10	0	0
T53	3535	22	0	0
T54	1938	4	0	0
T55	1514	8	0	0
T56	2844	8	0	0
T57	7221	6	0	0
T58	1811	4	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	694	0	0
T31	7434	69	0	0
T50	1657	4	0	0
T51	2920	65	0	0
T52	2471	17	0	0
T53	3535	18	0	0
T54	1938	5	0	0
T55	1514	17	0	0
T56	2844	17	0	0
T57	7221	8	0	0
T58	1811	9	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1343	0	0
T22	0	48	0	0
T48	421268	19	0	0
T49	113102	0	0	0
T59	0	25	0	0
T60	0	63	0	0
T61	0	65	0	0
T62	0	15	0	0
T63	0	52	0	0
T64	0	11	0	0
T65	0	20	0	0
T66	0	7	0	0
T67	171876	0	0	0
T68	164432	0	0	0
T69	263705	0	0	0
T70	113451	0	0	0
T71	708231	0	0	0
T72	145113	0	0	0
T73	153466	0	0	0
T74	354277	0	0	0