Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1670004	0	0
cfg0_rd_A	2147483647	8642	0	0
compare_lower0_0_rd_A	2147483647	9476	0	0
compare_upper0_0_rd_A	2147483647	8415	0	0
ctrl_rd_A	2147483647	8192	0	0
intr_enable0_rd_A	2147483647	10480	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1670004	0	0
T9	246957	102181	0	0
T10	287955	0	0	0
T11	0	124799	0	0
T12	0	254867	0	0
T32	0	56500	0	0
T33	0	128191	0	0
T34	0	267244	0	0
T35	0	103111	0	0
T36	0	54527	0	0
T37	0	44192	0	0
T38	0	404021	0	0
T39	230542	0	0	0
T40	542590	0	0	0
T41	180690	0	0	0
T42	688138	0	0	0
T43	209974	0	0	0
T44	833553	0	0	0
T45	169584	0	0	0
T46	8615	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8642	0	0
T11	479987	1227	0	0
T12	0	2483	0	0
T32	0	316	0	0
T34	0	2901	0	0
T36	0	209	0	0
T47	0	332	0	0
T48	0	17	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	25	0	0
T52	120494	0	0	0
T53	670132	0	0	0
T54	992603	0	0	0
T55	1492	0	0	0
T56	965596	0	0	0
T57	354564	0	0	0
T58	553671	0	0	0
T59	1364	0	0	0
T60	120095	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9476	0	0
T11	479987	1416	0	0
T12	0	2945	0	0
T32	0	349	0	0
T34	0	3241	0	0
T36	0	276	0	0
T47	0	330	0	0
T48	0	21	0	0
T50	0	2	0	0
T51	0	12	0	0
T52	120494	0	0	0
T53	670132	0	0	0
T54	992603	0	0	0
T55	1492	0	0	0
T56	965596	0	0	0
T57	354564	0	0	0
T58	553671	0	0	0
T59	1364	0	0	0
T60	120095	0	0	0
T61	0	2	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8415	0	0
T11	479987	1242	0	0
T12	0	2579	0	0
T32	0	347	0	0
T34	0	2741	0	0
T36	0	296	0	0
T47	0	218	0	0
T48	0	20	0	0
T51	0	10	0	0
T52	120494	0	0	0
T53	670132	0	0	0
T54	992603	0	0	0
T55	1492	0	0	0
T56	965596	0	0	0
T57	354564	0	0	0
T58	553671	0	0	0
T59	1364	0	0	0
T60	120095	0	0	0
T62	0	15	0	0
T63	0	53	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8192	0	0
T11	479987	1152	0	0
T12	0	2554	0	0
T32	0	262	0	0
T34	0	2823	0	0
T36	0	233	0	0
T47	0	242	0	0
T48	0	26	0	0
T51	0	4	0	0
T52	120494	0	0	0
T53	670132	0	0	0
T54	992603	0	0	0
T55	1492	0	0	0
T56	965596	0	0	0
T57	354564	0	0	0
T58	553671	0	0	0
T59	1364	0	0	0
T60	120095	0	0	0
T62	0	18	0	0
T64	0	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10480	0	0
T7	366798	76	0	0
T8	118357	0	0	0
T9	246957	0	0	0
T10	287955	0	0	0
T11	0	1516	0	0
T12	0	3066	0	0
T39	230542	0	0	0
T40	542590	0	0	0
T41	180690	0	0	0
T42	688138	0	0	0
T43	209974	0	0	0
T44	833553	0	0	0
T65	0	27	0	0
T66	0	28	0	0
T67	0	29	0	0
T68	0	43	0	0
T69	0	74	0	0
T70	0	18	0	0
T71	0	19	0	0