Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 55227624 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 56447670 1 T1 2066 T2 29203 T3 47985



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 110626865 1 T1 4054 T2 57760 T3 96410
values[0x0] 498649 1 T1 22 T2 14 T3 16
values[0x1] 549780 1 T1 27 T2 17 T3 23



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 44106708 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 67568586 1 T1 2472 T2 34927 T3 57637



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 399069 1 T1 18 T2 254 T3 375
valid_sources[0x01] 312004 1 T1 14 T2 300 T3 351
valid_sources[0x02] 339512 1 T1 20 T2 438 T3 368
valid_sources[0x03] 316269 1 T1 15 T2 201 T3 395
valid_sources[0x04] 318273 1 T1 17 T2 69 T3 405
valid_sources[0x05] 859744 1 T1 21 T2 168 T3 401
valid_sources[0x06] 313625 1 T1 13 T2 141 T3 326
valid_sources[0x07] 372897 1 T1 6 T2 216 T3 279
valid_sources[0x08] 316244 1 T1 16 T2 198 T3 365
valid_sources[0x09] 314925 1 T1 22 T2 271 T3 350
valid_sources[0x0a] 312053 1 T1 17 T2 292 T3 321
valid_sources[0x0b] 326364 1 T1 12 T2 300 T3 419
valid_sources[0x0c] 336003 1 T1 11 T2 331 T3 372
valid_sources[0x0d] 317806 1 T1 11 T2 273 T3 390
valid_sources[0x0e] 333569 1 T1 18 T2 205 T3 357
valid_sources[0x0f] 319657 1 T1 20 T2 193 T3 368
valid_sources[0x10] 316142 1 T1 27 T2 279 T3 327
valid_sources[0x11] 315135 1 T1 12 T2 123 T3 403
valid_sources[0x12] 319422 1 T1 16 T2 209 T3 423
valid_sources[0x13] 315541 1 T1 4 T2 113 T3 385
valid_sources[0x14] 319033 1 T1 11 T2 220 T3 380
valid_sources[0x15] 319459 1 T1 14 T2 142 T3 362
valid_sources[0x16] 2728661 1 T1 7 T2 220 T3 359
valid_sources[0x17] 348953 1 T1 13 T2 236 T3 340
valid_sources[0x18] 316243 1 T1 15 T2 195 T3 399
valid_sources[0x19] 316036 1 T1 12 T2 160 T3 394
valid_sources[0x1a] 314825 1 T1 21 T2 118 T3 385
valid_sources[0x1b] 1062547 1 T1 18 T2 550 T3 401
valid_sources[0x1c] 363789 1 T1 18 T2 227 T3 382
valid_sources[0x1d] 2153855 1 T1 17 T2 216 T3 384
valid_sources[0x1e] 317027 1 T1 10 T2 244 T3 300
valid_sources[0x1f] 315783 1 T1 12 T2 168 T3 420
valid_sources[0x20] 313240 1 T1 9 T2 246 T3 375
valid_sources[0x21] 637275 1 T1 8 T2 200 T3 410
valid_sources[0x22] 313449 1 T1 17 T2 146 T3 349
valid_sources[0x23] 316597 1 T1 6 T2 232 T3 414
valid_sources[0x24] 317566 1 T1 13 T2 440 T3 349
valid_sources[0x25] 322258 1 T1 26 T2 217 T3 375
valid_sources[0x26] 314285 1 T1 14 T2 66 T3 354
valid_sources[0x27] 316614 1 T1 13 T2 45 T3 350
valid_sources[0x28] 314375 1 T1 14 T2 96 T3 340
valid_sources[0x29] 318252 1 T1 11 T2 278 T3 383
valid_sources[0x2a] 766123 1 T1 14 T2 337 T3 422
valid_sources[0x2b] 319051 1 T1 14 T2 357 T3 426
valid_sources[0x2c] 959966 1 T1 21 T2 299 T3 417
valid_sources[0x2d] 315289 1 T1 17 T2 220 T3 359
valid_sources[0x2e] 317150 1 T1 18 T2 135 T3 408
valid_sources[0x2f] 318102 1 T1 14 T2 201 T3 354
valid_sources[0x30] 313760 1 T1 11 T2 286 T3 399
valid_sources[0x31] 313871 1 T1 21 T2 287 T3 409
valid_sources[0x32] 323570 1 T1 21 T2 198 T3 402
valid_sources[0x33] 316543 1 T1 13 T2 311 T3 422
valid_sources[0x34] 325852 1 T1 23 T2 117 T3 407
valid_sources[0x35] 315940 1 T1 33 T2 108 T3 386
valid_sources[0x36] 318953 1 T1 18 T2 460 T3 392
valid_sources[0x37] 311204 1 T1 19 T2 281 T3 392
valid_sources[0x38] 316920 1 T1 16 T2 422 T3 397
valid_sources[0x39] 319977 1 T1 12 T2 196 T3 339
valid_sources[0x3a] 318515 1 T1 15 T2 178 T3 374
valid_sources[0x3b] 316956 1 T1 14 T2 353 T3 455
valid_sources[0x3c] 315724 1 T1 15 T2 156 T3 449
valid_sources[0x3d] 316155 1 T1 10 T2 282 T3 414
valid_sources[0x3e] 312708 1 T1 22 T2 257 T3 368
valid_sources[0x3f] 315936 1 T1 7 T2 228 T3 388
valid_sources[0x40] 318164 1 T1 17 T2 245 T3 428
valid_sources[0x41] 317900 1 T1 19 T2 233 T3 348
valid_sources[0x42] 316066 1 T1 26 T2 167 T3 358
valid_sources[0x43] 452276 1 T1 21 T2 283 T3 320
valid_sources[0x44] 317282 1 T1 14 T2 222 T3 339
valid_sources[0x45] 364400 1 T1 14 T2 177 T3 420
valid_sources[0x46] 797412 1 T1 20 T2 243 T3 369
valid_sources[0x47] 314368 1 T1 12 T2 191 T3 435
valid_sources[0x48] 1007642 1 T1 17 T2 171 T3 403
valid_sources[0x49] 889401 1 T1 11 T2 165 T3 399
valid_sources[0x4a] 1774471 1 T1 19 T2 140 T3 391
valid_sources[0x4b] 1876985 1 T1 14 T2 135 T3 337
valid_sources[0x4c] 313770 1 T1 15 T2 340 T3 366
valid_sources[0x4d] 320382 1 T1 12 T2 120 T3 359
valid_sources[0x4e] 313745 1 T1 14 T2 295 T3 339
valid_sources[0x4f] 541436 1 T1 17 T2 386 T3 415
valid_sources[0x50] 314160 1 T1 10 T2 205 T3 340
valid_sources[0x51] 312779 1 T1 11 T2 268 T3 364
valid_sources[0x52] 317820 1 T1 16 T2 177 T3 390
valid_sources[0x53] 425840 1 T1 15 T2 266 T3 444
valid_sources[0x54] 2257281 1 T1 14 T2 227 T3 426
valid_sources[0x55] 319716 1 T1 15 T2 269 T3 369
valid_sources[0x56] 316855 1 T1 22 T2 210 T3 335
valid_sources[0x57] 314827 1 T1 12 T2 162 T3 389
valid_sources[0x58] 316787 1 T1 16 T2 168 T3 416
valid_sources[0x59] 315700 1 T1 19 T2 190 T3 382
valid_sources[0x5a] 315817 1 T1 32 T2 356 T3 395
valid_sources[0x5b] 312905 1 T1 11 T2 174 T3 408
valid_sources[0x5c] 315274 1 T1 10 T2 173 T3 393
valid_sources[0x5d] 347491 1 T1 14 T2 231 T3 364
valid_sources[0x5e] 316514 1 T1 22 T2 64 T3 354
valid_sources[0x5f] 345298 1 T1 13 T2 474 T3 386
valid_sources[0x60] 315222 1 T1 16 T2 128 T3 350
valid_sources[0x61] 314738 1 T1 16 T2 234 T3 466
valid_sources[0x62] 314785 1 T1 10 T2 171 T3 392
valid_sources[0x63] 312565 1 T1 13 T2 416 T3 402
valid_sources[0x64] 312357 1 T1 11 T2 135 T3 346
valid_sources[0x65] 318710 1 T1 16 T2 177 T3 395
valid_sources[0x66] 315840 1 T1 11 T2 323 T3 426
valid_sources[0x67] 313531 1 T1 25 T2 238 T3 355
valid_sources[0x68] 312304 1 T1 15 T2 161 T3 387
valid_sources[0x69] 317405 1 T1 23 T2 136 T3 457
valid_sources[0x6a] 313149 1 T1 25 T2 330 T3 407
valid_sources[0x6b] 316556 1 T1 26 T2 290 T3 380
valid_sources[0x6c] 314980 1 T1 19 T2 98 T3 367
valid_sources[0x6d] 315884 1 T1 27 T2 213 T3 373
valid_sources[0x6e] 3369875 1 T1 25 T2 339 T3 372
valid_sources[0x6f] 315007 1 T1 20 T2 382 T3 401
valid_sources[0x70] 3289725 1 T1 15 T2 270 T3 373
valid_sources[0x71] 316044 1 T1 21 T2 433 T3 367
valid_sources[0x72] 316245 1 T1 10 T2 45 T3 347
valid_sources[0x73] 313449 1 T1 11 T2 172 T3 327
valid_sources[0x74] 316663 1 T1 12 T2 357 T3 400
valid_sources[0x75] 331871 1 T1 17 T2 382 T3 377
valid_sources[0x76] 313988 1 T1 15 T2 175 T3 356
valid_sources[0x77] 314888 1 T1 22 T2 314 T3 335
valid_sources[0x78] 317542 1 T1 16 T2 168 T3 384
valid_sources[0x79] 316713 1 T1 15 T2 109 T3 382
valid_sources[0x7a] 315338 1 T1 12 T2 295 T3 327
valid_sources[0x7b] 316251 1 T1 6 T2 252 T3 351
valid_sources[0x7c] 314934 1 T1 15 T2 87 T3 381
valid_sources[0x7d] 318928 1 T1 29 T2 282 T3 389
valid_sources[0x7e] 375899 1 T1 14 T2 394 T3 442
valid_sources[0x7f] 1097363 1 T1 27 T2 86 T3 377
valid_sources[0x80] 311389 1 T1 10 T2 113 T3 371



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 55471672 1 T1 2034 T2 29183 T3 47959
values[0x0] all_enables biggest_size 488733 1 T1 17 T2 10 T3 13
values[0x1] all_enables biggest_size 487265 1 T1 15 T2 10 T3 13

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%