Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1700246	0	0
cfg0_rd_A	2147483647	6590	0	0
compare_lower0_0_rd_A	2147483647	7253	0	0
compare_upper0_0_rd_A	2147483647	6174	0	0
ctrl_rd_A	2147483647	6773	0	0
intr_enable0_rd_A	2147483647	7970	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1700246	0	0
T6	902183	247951	0	0
T7	207885	0	0	0
T8	420695	0	0	0
T9	101118	0	0	0
T10	360536	0	0	0
T11	214136	86546	0	0
T12	0	45968	0	0
T34	0	66390	0	0
T35	0	229824	0	0
T36	0	86365	0	0
T37	0	150850	0	0
T38	0	139488	0	0
T39	0	66074	0	0
T40	0	422672	0	0
T41	471207	0	0	0
T42	11245	0	0	0
T43	351800	0	0	0
T44	215608	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6590	0	0
T6	902183	1266	0	0
T7	207885	0	0	0
T8	420695	0	0	0
T9	101118	0	0	0
T10	360536	0	0	0
T11	214136	0	0	0
T29	0	91	0	0
T35	0	1246	0	0
T36	0	910	0	0
T38	0	1306	0	0
T41	471207	0	0	0
T42	11245	0	0	0
T43	351800	0	0	0
T44	215608	0	0	0
T45	0	2	0	0
T46	0	26	0	0
T47	0	13	0	0
T48	0	5	0	0
T49	0	12	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7253	0	0
T6	902183	1505	0	0
T7	207885	0	0	0
T8	420695	0	0	0
T9	101118	0	0	0
T10	360536	0	0	0
T11	214136	0	0	0
T29	0	65	0	0
T35	0	1414	0	0
T36	0	963	0	0
T38	0	1578	0	0
T41	471207	0	0	0
T42	11245	0	0	0
T43	351800	0	0	0
T44	215608	0	0	0
T45	0	12	0	0
T46	0	14	0	0
T47	0	7	0	0
T48	0	1	0	0
T49	0	23	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6174	0	0
T6	902183	1233	0	0
T7	207885	0	0	0
T8	420695	0	0	0
T9	101118	0	0	0
T10	360536	0	0	0
T11	214136	0	0	0
T29	0	55	0	0
T35	0	1109	0	0
T36	0	916	0	0
T38	0	1242	0	0
T41	471207	0	0	0
T42	11245	0	0	0
T43	351800	0	0	0
T44	215608	0	0	0
T45	0	11	0	0
T46	0	14	0	0
T47	0	17	0	0
T49	0	17	0	0
T50	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6773	0	0
T6	902183	1273	0	0
T7	207885	0	0	0
T8	420695	0	0	0
T9	101118	0	0	0
T10	360536	0	0	0
T11	214136	0	0	0
T29	0	67	0	0
T35	0	1383	0	0
T36	0	967	0	0
T38	0	1427	0	0
T41	471207	0	0	0
T42	11245	0	0	0
T43	351800	0	0	0
T44	215608	0	0	0
T46	0	13	0	0
T47	0	9	0	0
T48	0	8	0	0
T49	0	26	0	0
T50	0	12	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7970	0	0
T6	902183	1771	0	0
T7	207885	0	0	0
T8	420695	0	0	0
T9	101118	0	0	0
T10	360536	20	0	0
T11	214136	0	0	0
T33	0	17	0	0
T35	0	1296	0	0
T36	0	1034	0	0
T38	0	1626	0	0
T41	471207	0	0	0
T42	11245	0	0	0
T43	351800	0	0	0
T44	215608	0	0	0
T51	0	60	0	0
T52	0	39	0	0
T53	0	31	0	0
T54	0	8	0	0