Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57129294	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	57915820	1		T1	439285		T2	20512		T3	946

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	114369211	1		T1	878177		T2	41156		T3	1804
values[0x0]	321537	1		T1	55		T2	12		T3	10
values[0x1]	354366	1		T1	53		T2	7		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45636721	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	69408393	1		T1	527253		T2	24602		T3	1119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	365928	1		T1	3399		T2	180		T3	7
valid_sources[0x01]	362085	1		T1	3525		T2	147		T3	5
valid_sources[0x02]	366358	1		T1	3259		T2	153		T3	9
valid_sources[0x03]	1033440	1		T1	3432		T2	167		T3	4
valid_sources[0x04]	603855	1		T1	3333		T2	155		T3	9
valid_sources[0x05]	361803	1		T1	3449		T2	141		T3	8
valid_sources[0x06]	364416	1		T1	3355		T2	158		T3	3
valid_sources[0x07]	362567	1		T1	3446		T2	180		T3	3
valid_sources[0x08]	365420	1		T1	3511		T2	167		T3	7
valid_sources[0x09]	363214	1		T1	3459		T2	159		T3	9
valid_sources[0x0a]	363049	1		T1	3440		T2	153		T3	7
valid_sources[0x0b]	377914	1		T1	3344		T2	174		T3	11
valid_sources[0x0c]	360921	1		T1	3404		T2	197		T3	5
valid_sources[0x0d]	386400	1		T1	3354		T2	178		T3	11
valid_sources[0x0e]	367184	1		T1	3296		T2	159		T3	11
valid_sources[0x0f]	359442	1		T1	3229		T2	179		T3	10
valid_sources[0x10]	363883	1		T1	3265		T2	168		T3	7
valid_sources[0x11]	1629738	1		T1	3368		T2	181		T3	5
valid_sources[0x12]	364771	1		T1	3527		T2	135		T3	9
valid_sources[0x13]	365153	1		T1	3450		T2	163		T3	4
valid_sources[0x14]	366494	1		T1	3569		T2	165		T3	5
valid_sources[0x15]	770118	1		T1	3356		T2	159		T3	10
valid_sources[0x16]	360453	1		T1	3489		T2	187		T3	4
valid_sources[0x17]	364961	1		T1	3560		T2	171		T3	5
valid_sources[0x18]	363491	1		T1	3311		T2	171		T3	9
valid_sources[0x19]	380997	1		T1	3467		T2	165		T3	3
valid_sources[0x1a]	386321	1		T1	3380		T2	163		T3	7
valid_sources[0x1b]	495517	1		T1	3512		T2	141		T3	14
valid_sources[0x1c]	365646	1		T1	3583		T2	170		T3	6
valid_sources[0x1d]	365926	1		T1	3412		T2	168		T3	7
valid_sources[0x1e]	528146	1		T1	3438		T2	163		T3	1
valid_sources[0x1f]	388541	1		T1	3581		T2	147		T3	6
valid_sources[0x20]	416718	1		T1	3498		T2	158		T3	3
valid_sources[0x21]	367038	1		T1	3469		T2	154		T3	6
valid_sources[0x22]	400016	1		T1	3438		T2	206		T3	6
valid_sources[0x23]	361607	1		T1	3385		T2	137		T3	7
valid_sources[0x24]	364944	1		T1	3484		T2	155		T3	9
valid_sources[0x25]	362533	1		T1	3469		T2	168		T3	5
valid_sources[0x26]	416530	1		T1	3336		T2	164		T3	2
valid_sources[0x27]	361515	1		T1	3507		T2	167		T3	7
valid_sources[0x28]	362977	1		T1	3463		T2	162		T3	9
valid_sources[0x29]	365444	1		T1	3539		T2	157		T3	11
valid_sources[0x2a]	363029	1		T1	3278		T2	157		T3	11
valid_sources[0x2b]	360641	1		T1	3430		T2	200		T3	5
valid_sources[0x2c]	362596	1		T1	3534		T2	152		T3	5
valid_sources[0x2d]	360051	1		T1	3458		T2	171		T3	4
valid_sources[0x2e]	363853	1		T1	3409		T2	186		T3	10
valid_sources[0x2f]	914691	1		T1	3368		T2	153		T3	8
valid_sources[0x30]	360994	1		T1	3406		T2	166		T3	7
valid_sources[0x31]	364603	1		T1	3431		T2	172		T3	12
valid_sources[0x32]	365808	1		T1	3446		T2	170		T3	5
valid_sources[0x33]	364572	1		T1	3508		T2	159		T3	2
valid_sources[0x34]	361766	1		T1	3372		T2	169		T3	8
valid_sources[0x35]	362544	1		T1	3523		T2	170		T3	4
valid_sources[0x36]	363086	1		T1	3514		T2	159		T3	2
valid_sources[0x37]	360494	1		T1	3411		T2	136		T3	6
valid_sources[0x38]	956071	1		T1	3519		T2	175		T3	7
valid_sources[0x39]	363186	1		T1	3366		T2	140		T4	952
valid_sources[0x3a]	702774	1		T1	3437		T2	157		T3	9
valid_sources[0x3b]	359813	1		T1	3503		T2	188		T3	12
valid_sources[0x3c]	364039	1		T1	3460		T2	147		T3	6
valid_sources[0x3d]	511814	1		T1	3612		T2	162		T3	6
valid_sources[0x3e]	362281	1		T1	3485		T2	167		T3	10
valid_sources[0x3f]	365133	1		T1	3416		T2	155		T3	11
valid_sources[0x40]	364013	1		T1	3569		T2	148		T3	8
valid_sources[0x41]	364233	1		T1	3361		T2	150		T3	2
valid_sources[0x42]	363945	1		T1	3441		T2	179		T3	7
valid_sources[0x43]	361821	1		T1	3514		T2	180		T3	6
valid_sources[0x44]	370620	1		T1	3505		T2	157		T3	4
valid_sources[0x45]	371141	1		T1	3412		T2	151		T3	10
valid_sources[0x46]	580411	1		T1	3518		T2	141		T3	2
valid_sources[0x47]	363914	1		T1	3430		T2	161		T3	6
valid_sources[0x48]	1030109	1		T1	3498		T2	121		T3	9
valid_sources[0x49]	360588	1		T1	3511		T2	144		T3	13
valid_sources[0x4a]	384827	1		T1	3334		T2	145		T3	6
valid_sources[0x4b]	1077134	1		T1	3277		T2	155		T3	10
valid_sources[0x4c]	362913	1		T1	3447		T2	156		T3	2
valid_sources[0x4d]	3329040	1		T1	3598		T2	158		T3	5
valid_sources[0x4e]	676995	1		T1	3279		T2	158		T3	7
valid_sources[0x4f]	361860	1		T1	3393		T2	140		T3	15
valid_sources[0x50]	363596	1		T1	3543		T2	135		T3	7
valid_sources[0x51]	424453	1		T1	3396		T2	159		T3	12
valid_sources[0x52]	363123	1		T1	3701		T2	166		T3	4
valid_sources[0x53]	382060	1		T1	3463		T2	161		T3	6
valid_sources[0x54]	364519	1		T1	3319		T2	142		T3	11
valid_sources[0x55]	364184	1		T1	3424		T2	185		T3	5
valid_sources[0x56]	364654	1		T1	3414		T2	160		T3	4
valid_sources[0x57]	361430	1		T1	3612		T2	163		T3	11
valid_sources[0x58]	361797	1		T1	3396		T2	152		T3	3
valid_sources[0x59]	359884	1		T1	3326		T2	193		T3	4
valid_sources[0x5a]	361815	1		T1	3429		T2	150		T3	9
valid_sources[0x5b]	393820	1		T1	3419		T2	172		T3	5
valid_sources[0x5c]	364010	1		T1	3375		T2	158		T3	8
valid_sources[0x5d]	364710	1		T1	3575		T2	170		T3	1
valid_sources[0x5e]	361687	1		T1	3357		T2	146		T3	13
valid_sources[0x5f]	363577	1		T1	3363		T2	175		T3	13
valid_sources[0x60]	391404	1		T1	3379		T2	159		T3	5
valid_sources[0x61]	386105	1		T1	3460		T2	161		T3	4
valid_sources[0x62]	382614	1		T1	3370		T2	178		T3	7
valid_sources[0x63]	449459	1		T1	3432		T2	149		T3	5
valid_sources[0x64]	362143	1		T1	3416		T2	203		T3	9
valid_sources[0x65]	674864	1		T1	3321		T2	178		T3	8
valid_sources[0x66]	361562	1		T1	3169		T2	156		T3	3
valid_sources[0x67]	359817	1		T1	3392		T2	153		T3	4
valid_sources[0x68]	363955	1		T1	3471		T2	147		T3	7
valid_sources[0x69]	600213	1		T1	3508		T2	153		T3	8
valid_sources[0x6a]	363181	1		T1	3306		T2	137		T3	3
valid_sources[0x6b]	465243	1		T1	3418		T2	144		T3	8
valid_sources[0x6c]	393418	1		T1	3558		T2	162		T3	6
valid_sources[0x6d]	360302	1		T1	3550		T2	154		T3	3
valid_sources[0x6e]	365566	1		T1	3306		T2	161		T3	9
valid_sources[0x6f]	362163	1		T1	3466		T2	167		T3	13
valid_sources[0x70]	368914	1		T1	3670		T2	155		T3	7
valid_sources[0x71]	364019	1		T1	3498		T2	161		T3	6
valid_sources[0x72]	407466	1		T1	3317		T2	184		T3	5
valid_sources[0x73]	361928	1		T1	3532		T2	159		T3	7
valid_sources[0x74]	363565	1		T1	3418		T2	155		T3	4
valid_sources[0x75]	364366	1		T1	3338		T2	149		T3	11
valid_sources[0x76]	365404	1		T1	3322		T2	173		T3	5
valid_sources[0x77]	361265	1		T1	3339		T2	151		T3	11
valid_sources[0x78]	358916	1		T1	3300		T2	154		T3	5
valid_sources[0x79]	1388053	1		T1	3401		T2	171		T3	7
valid_sources[0x7a]	369907	1		T1	3289		T2	143		T3	8
valid_sources[0x7b]	717418	1		T1	3493		T2	186		T3	7
valid_sources[0x7c]	582461	1		T1	3416		T2	202		T3	3
valid_sources[0x7d]	365215	1		T1	3382		T2	164		T3	4
valid_sources[0x7e]	364889	1		T1	3615		T2	146		T3	5
valid_sources[0x7f]	364343	1		T1	3463		T2	172		T3	9
valid_sources[0x80]	391336	1		T1	3453		T2	147		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

57291425

1

T1

439219

T2

20500

T3

936

values[0x0]

all_enables

biggest_size

313296

1

T1

30

T2

9

T3

6

values[0x1]

all_enables

biggest_size

311099

1

T1

36

T2

3

T3

4