Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1073960	0	0
cfg0_rd_A	2147483647	3180	0	0
compare_lower0_0_rd_A	2147483647	3537	0	0
compare_upper0_0_rd_A	2147483647	3105	0	0
ctrl_rd_A	2147483647	3266	0	0
intr_enable0_rd_A	2147483647	3973	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073960	0	0
T13	147273	348064	0	0
T14	0	91058	0	0
T15	0	61599	0	0
T23	0	5	0	0
T27	0	66403	0	0
T28	0	54811	0	0
T29	0	43455	0	0
T30	0	94185	0	0
T31	0	54761	0	0
T32	0	247683	0	0
T33	730208	0	0	0
T34	130092	0	0	0
T35	171856	0	0	0
T36	151731	0	0	0
T37	331464	0	0	0
T38	557906	0	0	0
T39	303418	0	0	0
T40	636695	0	0	0
T41	690182	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3180	0	0
T15	225470	354	0	0
T23	0	70	0	0
T27	219877	0	0	0
T28	0	472	0	0
T30	0	891	0	0
T31	0	622	0	0
T42	0	2	0	0
T43	0	8	0	0
T44	0	21	0	0
T45	0	70	0	0
T46	0	11	0	0
T47	822611	0	0	0
T48	168331	0	0	0
T49	472944	0	0	0
T50	416269	0	0	0
T51	382826	0	0	0
T52	181506	0	0	0
T53	157942	0	0	0
T54	436072	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3537	0	0
T15	225470	341	0	0
T23	0	35	0	0
T27	219877	0	0	0
T28	0	669	0	0
T30	0	1145	0	0
T31	0	631	0	0
T42	0	4	0	0
T43	0	7	0	0
T44	0	49	0	0
T45	0	42	0	0
T46	0	9	0	0
T47	822611	0	0	0
T48	168331	0	0	0
T49	472944	0	0	0
T50	416269	0	0	0
T51	382826	0	0	0
T52	181506	0	0	0
T53	157942	0	0	0
T54	436072	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3105	0	0
T15	225470	347	0	0
T23	0	39	0	0
T27	219877	0	0	0
T28	0	582	0	0
T30	0	973	0	0
T31	0	512	0	0
T42	0	7	0	0
T43	0	12	0	0
T44	0	53	0	0
T45	0	38	0	0
T46	0	2	0	0
T47	822611	0	0	0
T48	168331	0	0	0
T49	472944	0	0	0
T50	416269	0	0	0
T51	382826	0	0	0
T52	181506	0	0	0
T53	157942	0	0	0
T54	436072	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3266	0	0
T15	225470	362	0	0
T23	0	37	0	0
T27	219877	0	0	0
T28	0	649	0	0
T30	0	957	0	0
T31	0	552	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	38	0	0
T45	0	106	0	0
T46	0	19	0	0
T47	822611	0	0	0
T48	168331	0	0	0
T49	472944	0	0	0
T50	416269	0	0	0
T51	382826	0	0	0
T52	181506	0	0	0
T53	157942	0	0	0
T54	436072	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3973	0	0
T1	254358	18	0	0
T2	903963	0	0	0
T3	442968	0	0	0
T4	584530	0	0	0
T5	471473	0	0	0
T6	6605	0	0	0
T7	111669	0	0	0
T8	308027	0	0	0
T9	379985	0	0	0
T10	459187	0	0	0
T11	0	16	0	0
T15	0	383	0	0
T28	0	691	0	0
T55	0	20	0	0
T56	0	53	0	0
T57	0	37	0	0
T58	0	42	0	0
T59	0	13	0	0
T60	0	51	0	0