Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1829252	0	0
cfg0_rd_A	2147483647	7595	0	0
compare_lower0_0_rd_A	2147483647	8696	0	0
compare_upper0_0_rd_A	2147483647	7544	0	0
ctrl_rd_A	2147483647	7065	0	0
intr_enable0_rd_A	2147483647	9444	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1829252	0	0
T15	563035	144133	0	0
T16	0	59876	0	0
T17	0	233472	0	0
T38	0	99737	0	0
T39	0	114979	0	0
T40	0	399627	0	0
T41	0	123876	0	0
T42	0	135958	0	0
T43	0	62785	0	0
T44	0	158001	0	0
T45	124264	0	0	0
T46	142290	0	0	0
T47	686703	0	0	0
T48	145326	0	0	0
T49	122208	0	0	0
T50	191264	0	0	0
T51	444145	0	0	0
T52	786142	0	0	0
T53	622511	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7595	0	0
T15	563035	1487	0	0
T33	0	50	0	0
T41	0	1280	0	0
T42	0	1274	0	0
T43	0	645	0	0
T44	0	867	0	0
T45	124264	0	0	0
T46	142290	0	0	0
T47	686703	0	0	0
T48	145326	0	0	0
T49	122208	0	0	0
T50	191264	0	0	0
T51	444145	0	0	0
T52	786142	0	0	0
T53	622511	0	0	0
T54	0	94	0	0
T55	0	43	0	0
T56	0	9	0	0
T57	0	49	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8696	0	0
T15	563035	1784	0	0
T33	0	33	0	0
T41	0	1498	0	0
T42	0	1829	0	0
T43	0	652	0	0
T44	0	941	0	0
T45	124264	0	0	0
T46	142290	0	0	0
T47	686703	0	0	0
T48	145326	0	0	0
T49	122208	0	0	0
T50	191264	0	0	0
T51	444145	0	0	0
T52	786142	0	0	0
T53	622511	0	0	0
T54	0	61	0	0
T55	0	4	0	0
T56	0	7	0	0
T57	0	44	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7544	0	0
T15	563035	1542	0	0
T33	0	25	0	0
T41	0	1325	0	0
T42	0	1227	0	0
T43	0	658	0	0
T44	0	855	0	0
T45	124264	0	0	0
T46	142290	0	0	0
T47	686703	0	0	0
T48	145326	0	0	0
T49	122208	0	0	0
T50	191264	0	0	0
T51	444145	0	0	0
T52	786142	0	0	0
T53	622511	0	0	0
T54	0	70	0	0
T55	0	39	0	0
T56	0	9	0	0
T57	0	41	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7065	0	0
T15	563035	1356	0	0
T33	0	53	0	0
T41	0	1196	0	0
T42	0	1243	0	0
T43	0	531	0	0
T44	0	828	0	0
T45	124264	0	0	0
T46	142290	0	0	0
T47	686703	0	0	0
T48	145326	0	0	0
T49	122208	0	0	0
T50	191264	0	0	0
T51	444145	0	0	0
T52	786142	0	0	0
T53	622511	0	0	0
T54	0	53	0	0
T55	0	2	0	0
T56	0	6	0	0
T57	0	101	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9444	0	0
T15	563035	1795	0	0
T31	0	17	0	0
T41	0	1592	0	0
T42	0	1672	0	0
T43	0	919	0	0
T44	0	964	0	0
T45	124264	0	0	0
T46	142290	0	0	0
T47	686703	0	0	0
T48	145326	0	0	0
T49	122208	0	0	0
T50	191264	0	0	0
T51	444145	0	0	0
T52	786142	0	0	0
T53	622511	0	0	0
T58	0	10	0	0
T59	0	37	0	0
T60	0	16	0	0
T61	0	17	0	0