Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1523303	0	0
cfg0_rd_A	2147483647	5359	0	0
compare_lower0_0_rd_A	2147483647	5164	0	0
compare_upper0_0_rd_A	2147483647	4513	0	0
ctrl_rd_A	2147483647	4933	0	0
intr_enable0_rd_A	2147483647	6545	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523303	0	0
T5	197272	60287	0	0
T6	815511	0	0	0
T7	238855	0	0	0
T8	725096	0	0	0
T9	653689	0	0	0
T10	274320	0	0	0
T11	8227	0	0	0
T12	169341	0	0	0
T13	0	96577	0	0
T14	0	61698	0	0
T34	0	45788	0	0
T35	0	56896	0	0
T36	0	82774	0	0
T37	0	136720	0	0
T38	0	92346	0	0
T39	0	66397	0	0
T40	0	109141	0	0
T41	422500	0	0	0
T42	435334	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5359	0	0
T13	416845	1143	0	0
T14	245002	613	0	0
T30	0	65	0	0
T35	0	717	0	0
T39	0	392	0	0
T43	0	9	0	0
T44	0	9	0	0
T45	0	20	0	0
T46	0	64	0	0
T47	0	78	0	0
T48	606695	0	0	0
T49	832948	0	0	0
T50	675958	0	0	0
T51	133135	0	0	0
T52	182892	0	0	0
T53	176600	0	0	0
T54	626016	0	0	0
T55	398774	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5164	0	0
T13	416845	1168	0	0
T14	245002	619	0	0
T30	0	34	0	0
T35	0	696	0	0
T39	0	397	0	0
T43	0	6	0	0
T45	0	14	0	0
T46	0	34	0	0
T47	0	45	0	0
T48	606695	0	0	0
T49	832948	0	0	0
T50	675958	0	0	0
T51	133135	0	0	0
T52	182892	0	0	0
T53	176600	0	0	0
T54	626016	0	0	0
T55	398774	0	0	0
T56	0	38	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4513	0	0
T13	416845	933	0	0
T14	245002	500	0	0
T30	0	42	0	0
T35	0	669	0	0
T39	0	311	0	0
T43	0	9	0	0
T44	0	3	0	0
T45	0	10	0	0
T46	0	53	0	0
T47	0	50	0	0
T48	606695	0	0	0
T49	832948	0	0	0
T50	675958	0	0	0
T51	133135	0	0	0
T52	182892	0	0	0
T53	176600	0	0	0
T54	626016	0	0	0
T55	398774	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4933	0	0
T13	416845	913	0	0
T14	245002	674	0	0
T30	0	37	0	0
T35	0	592	0	0
T39	0	390	0	0
T43	0	7	0	0
T45	0	18	0	0
T46	0	58	0	0
T47	0	65	0	0
T48	606695	0	0	0
T49	832948	0	0	0
T50	675958	0	0	0
T51	133135	0	0	0
T52	182892	0	0	0
T53	176600	0	0	0
T54	626016	0	0	0
T55	398774	0	0	0
T57	0	1	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6545	0	0
T13	0	1199	0	0
T14	0	790	0	0
T15	4468	0	0	0
T16	3352	0	0	0
T49	0	42	0	0
T58	419035	13	0	0
T59	0	67	0	0
T60	0	45	0	0
T61	0	79	0	0
T62	0	68	0	0
T63	0	94	0	0
T64	0	43	0	0
T65	378756	0	0	0
T66	456259	0	0	0
T67	676335	0	0	0
T68	221649	0	0	0
T69	915481	0	0	0
T70	141734	0	0	0
T71	912424	0	0	0