Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2009645	0	0
cfg0_rd_A	2147483647	11423	0	0
compare_lower0_0_rd_A	2147483647	11677	0	0
compare_upper0_0_rd_A	2147483647	10369	0	0
ctrl_rd_A	2147483647	10374	0	0
intr_enable0_rd_A	2147483647	13399	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2009645	0	0
T11	638759	162115	0	0
T12	576846	150386	0	0
T13	0	132748	0	0
T24	0	112887	0	0
T31	0	138540	0	0
T32	0	73472	0	0
T33	0	255227	0	0
T34	0	132859	0	0
T35	0	313425	0	0
T36	0	83834	0	0
T37	967954	0	0	0
T38	146431	0	0	0
T39	890332	0	0	0
T40	395801	0	0	0
T41	954828	0	0	0
T42	282216	0	0	0
T43	391813	0	0	0
T44	2744	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11423	0	0
T11	638759	1887	0	0
T12	576846	1507	0	0
T13	0	1461	0	0
T28	0	195	0	0
T32	0	617	0	0
T36	0	844	0	0
T37	967954	0	0	0
T38	146431	0	0	0
T39	890332	0	0	0
T40	395801	0	0	0
T41	954828	0	0	0
T42	282216	0	0	0
T43	391813	0	0	0
T44	2744	0	0	0
T45	0	1187	0	0
T46	0	601	0	0
T47	0	1195	0	0
T48	0	25	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11677	0	0
T11	638759	2025	0	0
T12	576846	1604	0	0
T13	0	1583	0	0
T28	0	120	0	0
T32	0	783	0	0
T36	0	917	0	0
T37	967954	0	0	0
T38	146431	0	0	0
T39	890332	0	0	0
T40	395801	0	0	0
T41	954828	0	0	0
T42	282216	0	0	0
T43	391813	0	0	0
T44	2744	0	0	0
T45	0	1057	0	0
T46	0	424	0	0
T47	0	1491	0	0
T48	0	10	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10369	0	0
T11	638759	1701	0	0
T12	576846	1507	0	0
T13	0	1242	0	0
T28	0	98	0	0
T32	0	665	0	0
T36	0	892	0	0
T37	967954	0	0	0
T38	146431	0	0	0
T39	890332	0	0	0
T40	395801	0	0	0
T41	954828	0	0	0
T42	282216	0	0	0
T43	391813	0	0	0
T44	2744	0	0	0
T45	0	988	0	0
T46	0	531	0	0
T47	0	1199	0	0
T48	0	3	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10374	0	0
T11	638759	1674	0	0
T12	576846	1569	0	0
T13	0	1370	0	0
T28	0	125	0	0
T32	0	645	0	0
T36	0	790	0	0
T37	967954	0	0	0
T38	146431	0	0	0
T39	890332	0	0	0
T40	395801	0	0	0
T41	954828	0	0	0
T42	282216	0	0	0
T43	391813	0	0	0
T44	2744	0	0	0
T45	0	1028	0	0
T46	0	451	0	0
T47	0	1190	0	0
T48	0	6	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13399	0	0
T11	638759	1873	0	0
T12	576846	1801	0	0
T13	0	1627	0	0
T23	0	26	0	0
T37	967954	0	0	0
T38	146431	0	0	0
T39	890332	0	0	0
T40	395801	0	0	0
T41	954828	0	0	0
T42	282216	0	0	0
T43	391813	0	0	0
T44	2744	0	0	0
T49	0	40	0	0
T50	0	30	0	0
T51	0	14	0	0
T52	0	35	0	0
T53	0	23	0	0
T54	0	37	0	0