Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1379317	0	0
cfg0_rd_A	2147483647	1460	0	0
compare_lower0_0_rd_A	2147483647	1528	0	0
compare_upper0_0_rd_A	2147483647	1412	0	0
ctrl_rd_A	2147483647	1525	0	0
intr_enable0_rd_A	2147483647	2122	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1379317	0	0
T10	194604	79058	0	0
T11	171614	52547	0	0
T12	0	35132	0	0
T32	203756	0	0	0
T33	0	48250	0	0
T34	0	118866	0	0
T35	0	92590	0	0
T36	0	57684	0	0
T37	0	199027	0	0
T38	0	173741	0	0
T39	0	34706	0	0
T40	199497	0	0	0
T41	867637	0	0	0
T42	218917	0	0	0
T43	362204	0	0	0
T44	224793	0	0	0
T45	589949	0	0	0
T46	170576	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1460	0	0
T36	209934	217	0	0
T37	469315	0	0	0
T39	0	324	0	0
T47	0	39	0	0
T48	0	75	0	0
T49	0	48	0	0
T50	0	60	0	0
T51	0	7	0	0
T52	0	6	0	0
T53	0	19	0	0
T54	0	4	0	0
T55	134065	0	0	0
T56	213004	0	0	0
T57	628649	0	0	0
T58	494573	0	0	0
T59	172259	0	0	0
T60	687731	0	0	0
T61	182278	0	0	0
T62	699322	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1528	0	0
T36	209934	309	0	0
T37	469315	0	0	0
T39	0	383	0	0
T47	0	16	0	0
T48	0	137	0	0
T49	0	10	0	0
T50	0	55	0	0
T52	0	3	0	0
T53	0	17	0	0
T54	0	2	0	0
T55	134065	0	0	0
T56	213004	0	0	0
T57	628649	0	0	0
T58	494573	0	0	0
T59	172259	0	0	0
T60	687731	0	0	0
T61	182278	0	0	0
T62	699322	0	0	0
T63	0	6	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1412	0	0
T36	209934	416	0	0
T37	469315	0	0	0
T39	0	290	0	0
T47	0	26	0	0
T48	0	124	0	0
T49	0	7	0	0
T50	0	28	0	0
T52	0	13	0	0
T53	0	16	0	0
T54	0	8	0	0
T55	134065	0	0	0
T56	213004	0	0	0
T57	628649	0	0	0
T58	494573	0	0	0
T59	172259	0	0	0
T60	687731	0	0	0
T61	182278	0	0	0
T62	699322	0	0	0
T63	0	12	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1525	0	0
T36	209934	323	0	0
T37	469315	0	0	0
T39	0	356	0	0
T47	0	20	0	0
T48	0	120	0	0
T49	0	27	0	0
T50	0	41	0	0
T52	0	21	0	0
T53	0	5	0	0
T54	0	4	0	0
T55	134065	0	0	0
T56	213004	0	0	0
T57	628649	0	0	0
T58	494573	0	0	0
T59	172259	0	0	0
T60	687731	0	0	0
T61	182278	0	0	0
T62	699322	0	0	0
T64	0	4	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2122	0	0
T36	0	381	0	0
T39	0	402	0	0
T65	730309	27	0	0
T66	527763	47	0	0
T67	0	24	0	0
T68	0	11	0	0
T69	0	13	0	0
T70	0	58	0	0
T71	0	20	0	0
T72	0	55	0	0
T73	110263	0	0	0
T74	956466	0	0	0
T75	131009	0	0	0
T76	166222	0	0	0
T77	990676	0	0	0
T78	210477	0	0	0
T79	140315	0	0	0
T80	514229	0	0	0