Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 62301361 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 63020736 1 T1 7976 T2 1079 T3 43567



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 124674796 1 T1 15723 T2 2115 T3 87212
values[0x0] 307070 1 T1 26 T2 23 T3 12
values[0x1] 340231 1 T1 25 T2 35 T3 8



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 49767351 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 75554746 1 T1 9552 T2 1303 T3 52298



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 365063 1 T2 6 T3 355 T4 207
valid_sources[0x01] 375016 1 T2 5 T3 296 T4 196
valid_sources[0x02] 390169 1 T2 1 T3 354 T4 184
valid_sources[0x03] 403615 1 T2 9 T3 375 T4 162
valid_sources[0x04] 647729 1 T2 15 T3 344 T4 216
valid_sources[0x05] 422265 1 T2 14 T3 377 T4 180
valid_sources[0x06] 1385314 1 T2 5 T3 363 T4 196
valid_sources[0x07] 368892 1 T2 13 T3 398 T4 205
valid_sources[0x08] 368107 1 T2 6 T3 373 T4 173
valid_sources[0x09] 1173735 1 T2 6 T3 366 T4 173
valid_sources[0x0a] 365029 1 T2 7 T3 334 T4 180
valid_sources[0x0b] 366008 1 T2 6 T3 346 T4 240
valid_sources[0x0c] 367025 1 T2 4 T3 345 T4 195
valid_sources[0x0d] 365668 1 T2 6 T3 324 T4 205
valid_sources[0x0e] 365069 1 T2 4 T3 313 T4 191
valid_sources[0x0f] 461987 1 T2 9 T3 351 T4 210
valid_sources[0x10] 367368 1 T2 14 T3 295 T4 171
valid_sources[0x11] 368158 1 T2 15 T3 368 T4 163
valid_sources[0x12] 366392 1 T2 3 T3 332 T4 177
valid_sources[0x13] 369281 1 T2 5 T3 352 T4 168
valid_sources[0x14] 369526 1 T2 11 T3 319 T4 232
valid_sources[0x15] 365572 1 T2 8 T3 317 T4 176
valid_sources[0x16] 365742 1 T2 5 T3 362 T4 164
valid_sources[0x17] 368318 1 T2 5 T3 321 T4 211
valid_sources[0x18] 1061496 1 T2 9 T3 365 T4 197
valid_sources[0x19] 592805 1 T2 18 T3 331 T4 222
valid_sources[0x1a] 376925 1 T2 10 T3 337 T4 225
valid_sources[0x1b] 365572 1 T2 2 T3 350 T4 149
valid_sources[0x1c] 366646 1 T2 9 T3 370 T4 158
valid_sources[0x1d] 1803303 1 T2 4 T3 394 T4 165
valid_sources[0x1e] 366710 1 T2 13 T3 338 T4 182
valid_sources[0x1f] 803393 1 T2 2 T3 353 T4 160
valid_sources[0x20] 367648 1 T2 9 T3 380 T4 174
valid_sources[0x21] 574048 1 T2 6 T3 343 T4 204
valid_sources[0x22] 368845 1 T2 14 T3 378 T4 140
valid_sources[0x23] 366246 1 T2 5 T3 367 T4 181
valid_sources[0x24] 361250 1 T2 5 T3 335 T4 166
valid_sources[0x25] 581901 1 T2 8 T3 304 T4 193
valid_sources[0x26] 1727306 1 T2 5 T3 315 T4 182
valid_sources[0x27] 363671 1 T2 3 T3 310 T4 171
valid_sources[0x28] 363682 1 T2 8 T3 333 T4 130
valid_sources[0x29] 365062 1 T2 12 T3 333 T4 201
valid_sources[0x2a] 784337 1 T2 4 T3 351 T4 146
valid_sources[0x2b] 367951 1 T2 13 T3 348 T4 151
valid_sources[0x2c] 368223 1 T2 12 T3 348 T4 234
valid_sources[0x2d] 369041 1 T2 14 T3 316 T4 184
valid_sources[0x2e] 363530 1 T2 14 T3 396 T4 150
valid_sources[0x2f] 374587 1 T2 5 T3 359 T4 165
valid_sources[0x30] 367099 1 T2 6 T3 313 T4 186
valid_sources[0x31] 364499 1 T2 10 T3 319 T4 181
valid_sources[0x32] 366827 1 T2 8 T3 366 T4 198
valid_sources[0x33] 364887 1 T2 11 T3 333 T4 200
valid_sources[0x34] 367370 1 T2 12 T3 333 T4 184
valid_sources[0x35] 655853 1 T2 6 T3 341 T4 223
valid_sources[0x36] 376204 1 T2 5 T3 364 T4 183
valid_sources[0x37] 363894 1 T2 8 T3 346 T4 205
valid_sources[0x38] 366878 1 T2 17 T3 366 T4 143
valid_sources[0x39] 365651 1 T2 7 T3 353 T4 183
valid_sources[0x3a] 369306 1 T2 15 T3 343 T4 167
valid_sources[0x3b] 627993 1 T2 14 T3 348 T4 169
valid_sources[0x3c] 364806 1 T2 4 T3 336 T4 189
valid_sources[0x3d] 1028770 1 T2 6 T3 356 T4 194
valid_sources[0x3e] 374755 1 T2 4 T3 354 T4 195
valid_sources[0x3f] 611049 1 T2 6 T3 330 T4 177
valid_sources[0x40] 366458 1 T2 13 T3 324 T4 179
valid_sources[0x41] 541985 1 T2 12 T3 351 T4 227
valid_sources[0x42] 368011 1 T2 9 T3 360 T4 129
valid_sources[0x43] 1440255 1 T2 12 T3 331 T4 221
valid_sources[0x44] 365132 1 T2 2 T3 358 T4 174
valid_sources[0x45] 365200 1 T2 5 T3 330 T4 182
valid_sources[0x46] 368813 1 T2 13 T3 371 T4 195
valid_sources[0x47] 363677 1 T2 8 T3 314 T4 218
valid_sources[0x48] 506555 1 T2 11 T3 341 T4 226
valid_sources[0x49] 366430 1 T2 4 T3 322 T4 208
valid_sources[0x4a] 369455 1 T2 8 T3 321 T4 205
valid_sources[0x4b] 433615 1 T2 13 T3 334 T4 226
valid_sources[0x4c] 366565 1 T2 7 T3 304 T4 162
valid_sources[0x4d] 369809 1 T2 8 T3 329 T4 216
valid_sources[0x4e] 365529 1 T2 6 T3 351 T4 197
valid_sources[0x4f] 391664 1 T2 5 T3 342 T4 169
valid_sources[0x50] 367283 1 T2 13 T3 330 T4 189
valid_sources[0x51] 368385 1 T2 4 T3 317 T4 204
valid_sources[0x52] 365731 1 T2 9 T3 355 T4 191
valid_sources[0x53] 364928 1 T2 14 T3 351 T4 150
valid_sources[0x54] 370029 1 T2 8 T3 344 T4 138
valid_sources[0x55] 366969 1 T2 10 T3 335 T4 199
valid_sources[0x56] 367180 1 T2 7 T3 396 T4 161
valid_sources[0x57] 369460 1 T2 9 T3 342 T4 172
valid_sources[0x58] 366470 1 T2 5 T3 365 T4 194
valid_sources[0x59] 1969644 1 T2 6 T3 340 T4 204
valid_sources[0x5a] 367503 1 T2 5 T3 343 T4 223
valid_sources[0x5b] 365018 1 T2 20 T3 355 T4 181
valid_sources[0x5c] 366537 1 T2 12 T3 294 T4 160
valid_sources[0x5d] 370173 1 T2 5 T3 360 T4 201
valid_sources[0x5e] 365884 1 T2 7 T3 303 T4 175
valid_sources[0x5f] 460557 1 T2 6 T3 333 T4 272
valid_sources[0x60] 367020 1 T2 10 T3 347 T4 218
valid_sources[0x61] 366024 1 T2 6 T3 324 T4 167
valid_sources[0x62] 365910 1 T2 17 T3 362 T4 197
valid_sources[0x63] 363913 1 T2 3 T3 333 T4 177
valid_sources[0x64] 381296 1 T2 4 T3 297 T4 172
valid_sources[0x65] 365686 1 T2 8 T3 345 T4 192
valid_sources[0x66] 928548 1 T2 7 T3 314 T4 202
valid_sources[0x67] 366979 1 T2 13 T3 292 T4 224
valid_sources[0x68] 365370 1 T2 4 T3 336 T4 168
valid_sources[0x69] 1424955 1 T2 4 T3 318 T4 192
valid_sources[0x6a] 365810 1 T2 6 T3 318 T4 184
valid_sources[0x6b] 594871 1 T2 5 T3 347 T4 182
valid_sources[0x6c] 366142 1 T2 16 T3 292 T4 165
valid_sources[0x6d] 390761 1 T2 6 T3 349 T4 169
valid_sources[0x6e] 367222 1 T2 13 T3 339 T4 141
valid_sources[0x6f] 366209 1 T2 4 T3 348 T4 190
valid_sources[0x70] 538237 1 T2 5 T3 352 T4 135
valid_sources[0x71] 368576 1 T2 10 T3 343 T4 168
valid_sources[0x72] 367209 1 T2 6 T3 333 T4 203
valid_sources[0x73] 368130 1 T2 6 T3 345 T4 184
valid_sources[0x74] 370414 1 T2 6 T3 319 T4 261
valid_sources[0x75] 369513 1 T2 8 T3 314 T4 167
valid_sources[0x76] 365693 1 T2 8 T3 344 T4 269
valid_sources[0x77] 368078 1 T2 7 T3 335 T4 143
valid_sources[0x78] 368843 1 T2 13 T3 340 T4 173
valid_sources[0x79] 367083 1 T2 7 T3 355 T4 210
valid_sources[0x7a] 367727 1 T2 12 T3 315 T4 196
valid_sources[0x7b] 1012871 1 T2 12 T3 368 T4 190
valid_sources[0x7c] 420077 1 T2 10 T3 323 T4 216
valid_sources[0x7d] 1107784 1 T2 4 T3 356 T4 216
valid_sources[0x7e] 367620 1 T2 9 T3 332 T4 190
valid_sources[0x7f] 360544 1 T2 4 T3 351 T4 201
valid_sources[0x80] 405361 1 T2 11 T3 347 T4 171



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 62423923 1 T1 7941 T2 1044 T3 43552
values[0x0] all_enables biggest_size 298582 1 T1 19 T2 15 T3 10
values[0x1] all_enables biggest_size 298231 1 T1 16 T2 20 T3 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%