Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1034459	0	0
cfg0_rd_A	2147483647	2983	0	0
compare_lower0_0_rd_A	2147483647	3121	0	0
compare_upper0_0_rd_A	2147483647	2782	0	0
ctrl_rd_A	2147483647	2840	0	0
intr_enable0_rd_A	2147483647	3724	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1034459	0	0
T11	908390	277720	0	0
T12	0	60734	0	0
T13	0	49113	0	0
T34	105208	0	0	0
T35	383043	0	0	0
T36	0	191485	0	0
T37	0	66490	0	0
T38	0	10595	0	0
T39	0	60135	0	0
T40	0	41326	0	0
T41	0	181161	0	0
T42	0	57876	0	0
T43	128667	0	0	0
T44	252176	0	0	0
T45	149469	0	0	0
T46	107565	0	0	0
T47	211492	0	0	0
T48	457595	0	0	0
T49	827775	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2983	0	0
T37	244833	674	0	0
T38	259875	0	0	0
T40	0	422	0	0
T50	0	299	0	0
T51	0	7	0	0
T52	0	3	0	0
T53	0	5	0	0
T54	0	27	0	0
T55	0	10	0	0
T56	0	17	0	0
T57	0	29	0	0
T58	467733	0	0	0
T59	103070	0	0	0
T60	118656	0	0	0
T61	946546	0	0	0
T62	303685	0	0	0
T63	820741	0	0	0
T64	186987	0	0	0
T65	971797	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3121	0	0
T37	244833	879	0	0
T38	259875	0	0	0
T40	0	442	0	0
T50	0	270	0	0
T51	0	8	0	0
T53	0	51	0	0
T54	0	49	0	0
T56	0	10	0	0
T57	0	24	0	0
T58	467733	0	0	0
T59	103070	0	0	0
T60	118656	0	0	0
T61	946546	0	0	0
T62	303685	0	0	0
T63	820741	0	0	0
T64	186987	0	0	0
T65	971797	0	0	0
T66	0	5	0	0
T67	0	76	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2782	0	0
T37	244833	578	0	0
T38	259875	0	0	0
T40	0	362	0	0
T50	0	290	0	0
T51	0	8	0	0
T53	0	26	0	0
T54	0	80	0	0
T55	0	2	0	0
T56	0	16	0	0
T57	0	52	0	0
T58	467733	0	0	0
T59	103070	0	0	0
T60	118656	0	0	0
T61	946546	0	0	0
T62	303685	0	0	0
T63	820741	0	0	0
T64	186987	0	0	0
T65	971797	0	0	0
T66	0	48	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2840	0	0
T37	244833	692	0	0
T38	259875	0	0	0
T40	0	420	0	0
T50	0	216	0	0
T51	0	6	0	0
T52	0	6	0	0
T53	0	42	0	0
T54	0	105	0	0
T56	0	3	0	0
T57	0	17	0	0
T58	467733	0	0	0
T59	103070	0	0	0
T60	118656	0	0	0
T61	946546	0	0	0
T62	303685	0	0	0
T63	820741	0	0	0
T64	186987	0	0	0
T65	971797	0	0	0
T66	0	4	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3724	0	0
T37	244833	842	0	0
T38	259875	0	0	0
T40	0	559	0	0
T50	0	387	0	0
T51	0	17	0	0
T58	467733	0	0	0
T59	103070	0	0	0
T60	118656	0	0	0
T61	946546	0	0	0
T62	303685	0	0	0
T63	820741	0	0	0
T64	186987	0	0	0
T65	971797	0	0	0
T68	0	14	0	0
T69	0	26	0	0
T70	0	79	0	0
T71	0	45	0	0
T72	0	12	0	0
T73	0	129	0	0