Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1905158	0	0
cfg0_rd_A	2147483647	5872	0	0
compare_lower0_0_rd_A	2147483647	6062	0	0
compare_upper0_0_rd_A	2147483647	5849	0	0
ctrl_rd_A	2147483647	5919	0	0
intr_enable0_rd_A	2147483647	7264	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1905158	0	0
T11	838518	222746	0	0
T12	0	217265	0	0
T13	0	46819	0	0
T24	0	109578	0	0
T32	0	279197	0	0
T33	0	60100	0	0
T34	0	54610	0	0
T35	0	77314	0	0
T36	0	118944	0	0
T37	0	20158	0	0
T38	358665	0	0	0
T39	106010	0	0	0
T40	957355	0	0	0
T41	797298	0	0	0
T42	295835	0	0	0
T43	109588	0	0	0
T44	311577	0	0	0
T45	281134	0	0	0
T46	325993	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5872	0	0
T13	172529	483	0	0
T24	0	638	0	0
T33	0	286	0	0
T34	0	548	0	0
T36	0	683	0	0
T37	0	199	0	0
T47	0	191	0	0
T48	0	574	0	0
T49	0	17	0	0
T50	0	407	0	0
T51	117901	0	0	0
T52	758440	0	0	0
T53	178345	0	0	0
T54	423296	0	0	0
T55	332640	0	0	0
T56	111201	0	0	0
T57	623252	0	0	0
T58	803180	0	0	0
T59	407743	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6062	0	0
T13	172529	441	0	0
T24	0	663	0	0
T33	0	294	0	0
T34	0	615	0	0
T36	0	717	0	0
T37	0	351	0	0
T47	0	196	0	0
T48	0	701	0	0
T49	0	11	0	0
T50	0	362	0	0
T51	117901	0	0	0
T52	758440	0	0	0
T53	178345	0	0	0
T54	423296	0	0	0
T55	332640	0	0	0
T56	111201	0	0	0
T57	623252	0	0	0
T58	803180	0	0	0
T59	407743	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5849	0	0
T13	172529	512	0	0
T24	0	624	0	0
T33	0	301	0	0
T34	0	562	0	0
T36	0	720	0	0
T37	0	142	0	0
T47	0	213	0	0
T48	0	508	0	0
T49	0	23	0	0
T50	0	435	0	0
T51	117901	0	0	0
T52	758440	0	0	0
T53	178345	0	0	0
T54	423296	0	0	0
T55	332640	0	0	0
T56	111201	0	0	0
T57	623252	0	0	0
T58	803180	0	0	0
T59	407743	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5919	0	0
T13	172529	550	0	0
T24	0	650	0	0
T33	0	375	0	0
T34	0	601	0	0
T36	0	516	0	0
T37	0	191	0	0
T47	0	273	0	0
T48	0	563	0	0
T49	0	15	0	0
T50	0	411	0	0
T51	117901	0	0	0
T52	758440	0	0	0
T53	178345	0	0	0
T54	423296	0	0	0
T55	332640	0	0	0
T56	111201	0	0	0
T57	623252	0	0	0
T58	803180	0	0	0
T59	407743	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7264	0	0
T10	143712	9	0	0
T13	0	624	0	0
T24	0	673	0	0
T33	0	361	0	0
T34	0	588	0	0
T60	457742	41	0	0
T61	0	12	0	0
T62	0	25	0	0
T63	0	34	0	0
T64	0	57	0	0
T65	936453	0	0	0
T66	132177	0	0	0
T67	261994	0	0	0
T68	330663	0	0	0
T69	450440	0	0	0
T70	141560	0	0	0
T71	455333	0	0	0
T72	426416	0	0	0