Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1798160	0	0
cfg0_rd_A	2147483647	6415	0	0
compare_lower0_0_rd_A	2147483647	6698	0	0
compare_upper0_0_rd_A	2147483647	6076	0	0
ctrl_rd_A	2147483647	6252	0	0
intr_enable0_rd_A	2147483647	8524	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1798160	0	0
T2	432850	181621	0	0
T3	381356	0	0	0
T4	617788	0	0	0
T5	432241	0	0	0
T6	291534	0	0	0
T7	387230	0	0	0
T8	508895	0	0	0
T9	256465	0	0	0
T10	733320	0	0	0
T11	111994	0	0	0
T13	0	44893	0	0
T14	0	61117	0	0
T33	0	45365	0	0
T34	0	48413	0	0
T35	0	91809	0	0
T36	0	175913	0	0
T37	0	35883	0	0
T38	0	57900	0	0
T39	0	352244	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6415	0	0
T14	230739	610	0	0
T29	0	82	0	0
T33	0	464	0	0
T34	0	428	0	0
T37	0	194	0	0
T38	0	540	0	0
T40	0	2374	0	0
T41	0	131	0	0
T42	0	170	0	0
T43	0	59	0	0
T44	7423	0	0	0
T45	391137	0	0	0
T46	176701	0	0	0
T47	271135	0	0	0
T48	464775	0	0	0
T49	842212	0	0	0
T50	109214	0	0	0
T51	585851	0	0	0
T52	735747	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6698	0	0
T14	230739	738	0	0
T29	0	88	0	0
T33	0	503	0	0
T34	0	476	0	0
T37	0	222	0	0
T38	0	678	0	0
T40	0	2540	0	0
T41	0	67	0	0
T42	0	117	0	0
T43	0	32	0	0
T44	7423	0	0	0
T45	391137	0	0	0
T46	176701	0	0	0
T47	271135	0	0	0
T48	464775	0	0	0
T49	842212	0	0	0
T50	109214	0	0	0
T51	585851	0	0	0
T52	735747	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6076	0	0
T14	230739	757	0	0
T29	0	44	0	0
T33	0	419	0	0
T34	0	430	0	0
T37	0	170	0	0
T38	0	500	0	0
T40	0	2296	0	0
T41	0	63	0	0
T42	0	127	0	0
T43	0	47	0	0
T44	7423	0	0	0
T45	391137	0	0	0
T46	176701	0	0	0
T47	271135	0	0	0
T48	464775	0	0	0
T49	842212	0	0	0
T50	109214	0	0	0
T51	585851	0	0	0
T52	735747	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6252	0	0
T14	230739	678	0	0
T29	0	92	0	0
T33	0	439	0	0
T34	0	417	0	0
T37	0	220	0	0
T38	0	617	0	0
T40	0	2296	0	0
T41	0	41	0	0
T42	0	132	0	0
T43	0	28	0	0
T44	7423	0	0	0
T45	391137	0	0	0
T46	176701	0	0	0
T47	271135	0	0	0
T48	464775	0	0	0
T49	842212	0	0	0
T50	109214	0	0	0
T51	585851	0	0	0
T52	735747	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8524	0	0
T14	0	984	0	0
T24	0	25	0	0
T33	0	497	0	0
T34	0	590	0	0
T53	325802	101	0	0
T54	0	31	0	0
T55	0	46	0	0
T56	0	101	0	0
T57	0	25	0	0
T58	0	42	0	0
T59	512821	0	0	0
T60	163597	0	0	0
T61	464065	0	0	0
T62	370889	0	0	0
T63	3198	0	0	0
T64	231907	0	0	0
T65	1399	0	0	0
T66	115548	0	0	0
T67	175990	0	0	0