Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2301241	0	0
cfg0_rd_A	2147483647	4811	0	0
compare_lower0_0_rd_A	2147483647	4863	0	0
compare_upper0_0_rd_A	2147483647	4148	0	0
ctrl_rd_A	2147483647	4355	0	0
intr_enable0_rd_A	2147483647	5506	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2301241	0	0
T9	919598	242495	0	0
T10	939994	0	0	0
T11	0	150336	0	0
T12	0	48853	0	0
T29	464121	0	0	0
T34	0	174959	0	0
T35	0	21798	0	0
T36	0	217607	0	0
T37	0	53109	0	0
T38	0	65250	0	0
T39	0	90980	0	0
T40	0	244021	0	0
T41	271004	0	0	0
T42	159043	0	0	0
T43	982337	0	0	0
T44	489758	0	0	0
T45	294486	0	0	0
T46	923256	0	0	0
T47	685063	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4811	0	0
T14	3590	0	0	0
T27	0	127	0	0
T35	825124	262	0	0
T37	0	595	0	0
T38	0	639	0	0
T40	0	1393	0	0
T48	0	11	0	0
T49	0	13	0	0
T50	0	18	0	0
T51	0	254	0	0
T52	0	41	0	0
T53	404921	0	0	0
T54	211245	0	0	0
T55	460194	0	0	0
T56	338144	0	0	0
T57	832996	0	0	0
T58	104487	0	0	0
T59	390401	0	0	0
T60	511496	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4863	0	0
T14	3590	0	0	0
T27	0	74	0	0
T35	825124	266	0	0
T37	0	667	0	0
T38	0	820	0	0
T40	0	1471	0	0
T48	0	20	0	0
T49	0	3	0	0
T50	0	5	0	0
T51	0	249	0	0
T52	0	36	0	0
T53	404921	0	0	0
T54	211245	0	0	0
T55	460194	0	0	0
T56	338144	0	0	0
T57	832996	0	0	0
T58	104487	0	0	0
T59	390401	0	0	0
T60	511496	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4148	0	0
T14	3590	0	0	0
T27	0	58	0	0
T35	825124	224	0	0
T37	0	579	0	0
T38	0	594	0	0
T40	0	1185	0	0
T48	0	8	0	0
T49	0	6	0	0
T50	0	6	0	0
T51	0	232	0	0
T53	404921	0	0	0
T54	211245	0	0	0
T55	460194	0	0	0
T56	338144	0	0	0
T57	832996	0	0	0
T58	104487	0	0	0
T59	390401	0	0	0
T60	511496	0	0	0
T61	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4355	0	0
T14	3590	0	0	0
T27	0	79	0	0
T35	825124	273	0	0
T37	0	509	0	0
T38	0	637	0	0
T40	0	1241	0	0
T48	0	33	0	0
T49	0	6	0	0
T50	0	12	0	0
T51	0	218	0	0
T53	404921	0	0	0
T54	211245	0	0	0
T55	460194	0	0	0
T56	338144	0	0	0
T57	832996	0	0	0
T58	104487	0	0	0
T59	390401	0	0	0
T60	511496	0	0	0
T62	0	2	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5506	0	0
T33	485647	53	0	0
T35	0	293	0	0
T37	0	663	0	0
T38	0	758	0	0
T40	0	1487	0	0
T63	0	127	0	0
T64	0	11	0	0
T65	0	35	0	0
T66	0	86	0	0
T67	0	35	0	0
T68	143954	0	0	0
T69	487846	0	0	0
T70	627303	0	0	0
T71	159470	0	0	0
T72	137386	0	0	0
T73	252564	0	0	0
T74	601611	0	0	0
T75	105212	0	0	0
T76	420634	0	0	0