Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	71720588	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	72906496	1		T1	4619		T2	30171		T3	928578

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143614816	1		T1	9133		T2	60781		T3	185760
values[0x0]	482611	1		T1	2		T2	21		T3	23
values[0x1]	529657	1		T1	5		T2	11		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57281645	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	87345439	1		T1	5534		T2	36356		T3	111521

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	436915	1		T1	37		T2	278		T3	7150
valid_sources[0x01]	436402	1		T1	48		T2	287		T3	6853
valid_sources[0x02]	442725	1		T1	39		T2	271		T3	7132
valid_sources[0x03]	490970	1		T1	53		T2	206		T3	6978
valid_sources[0x04]	677196	1		T1	36		T2	277		T3	7507
valid_sources[0x05]	438178	1		T1	47		T2	247		T3	7081
valid_sources[0x06]	836586	1		T1	36		T2	279		T3	6867
valid_sources[0x07]	438809	1		T1	35		T2	210		T3	7077
valid_sources[0x08]	437477	1		T1	45		T2	267		T3	7125
valid_sources[0x09]	437781	1		T1	48		T2	209		T3	7546
valid_sources[0x0a]	435648	1		T1	45		T2	235		T3	7289
valid_sources[0x0b]	934737	1		T1	40		T2	202		T3	7395
valid_sources[0x0c]	437040	1		T1	24		T2	217		T3	7361
valid_sources[0x0d]	436162	1		T1	25		T2	183		T3	7051
valid_sources[0x0e]	439690	1		T1	43		T2	256		T3	6673
valid_sources[0x0f]	443179	1		T1	35		T2	248		T3	7355
valid_sources[0x10]	437900	1		T1	39		T2	242		T3	7284
valid_sources[0x11]	436337	1		T1	20		T2	267		T3	7285
valid_sources[0x12]	441155	1		T1	25		T2	214		T3	7414
valid_sources[0x13]	436474	1		T1	35		T2	260		T3	7243
valid_sources[0x14]	438837	1		T1	34		T2	275		T3	7156
valid_sources[0x15]	1710896	1		T1	48		T2	240		T3	6989
valid_sources[0x16]	436027	1		T1	42		T2	227		T3	7292
valid_sources[0x17]	440698	1		T1	29		T2	260		T3	7126
valid_sources[0x18]	438937	1		T1	33		T2	223		T3	7440
valid_sources[0x19]	438378	1		T1	42		T2	206		T3	7191
valid_sources[0x1a]	439539	1		T1	43		T2	231		T3	7084
valid_sources[0x1b]	440169	1		T1	27		T2	271		T3	6545
valid_sources[0x1c]	1888766	1		T1	20		T2	220		T3	7172
valid_sources[0x1d]	442976	1		T1	25		T2	194		T3	7132
valid_sources[0x1e]	535728	1		T1	33		T2	217		T3	6896
valid_sources[0x1f]	636002	1		T1	19		T2	183		T3	6997
valid_sources[0x20]	2244489	1		T1	48		T2	259		T3	7114
valid_sources[0x21]	436292	1		T1	33		T2	311		T3	7311
valid_sources[0x22]	442149	1		T1	36		T2	299		T3	7757
valid_sources[0x23]	781263	1		T1	52		T2	228		T3	7452
valid_sources[0x24]	448354	1		T1	54		T2	204		T3	7525
valid_sources[0x25]	487169	1		T1	25		T2	270		T3	6760
valid_sources[0x26]	436183	1		T1	31		T2	261		T3	7079
valid_sources[0x27]	438752	1		T1	46		T2	225		T3	7544
valid_sources[0x28]	439428	1		T1	46		T2	284		T3	7741
valid_sources[0x29]	443225	1		T1	40		T2	245		T3	7180
valid_sources[0x2a]	439862	1		T1	25		T2	200		T3	6946
valid_sources[0x2b]	435097	1		T1	30		T2	165		T3	6843
valid_sources[0x2c]	438774	1		T1	48		T2	215		T3	7203
valid_sources[0x2d]	439014	1		T1	37		T2	192		T3	7214
valid_sources[0x2e]	439232	1		T1	47		T2	188		T3	6952
valid_sources[0x2f]	440571	1		T1	52		T2	242		T3	6938
valid_sources[0x30]	464312	1		T1	43		T2	276		T3	7291
valid_sources[0x31]	441936	1		T1	21		T2	170		T3	7289
valid_sources[0x32]	439235	1		T1	37		T2	167		T3	7147
valid_sources[0x33]	439264	1		T1	31		T2	241		T3	7120
valid_sources[0x34]	454421	1		T1	28		T2	305		T3	7333
valid_sources[0x35]	441668	1		T1	32		T2	234		T3	6817
valid_sources[0x36]	436741	1		T1	31		T2	159		T3	7342
valid_sources[0x37]	438380	1		T1	25		T2	208		T3	7749
valid_sources[0x38]	437815	1		T1	27		T2	197		T3	6864
valid_sources[0x39]	546337	1		T1	43		T2	254		T3	7161
valid_sources[0x3a]	437084	1		T1	37		T2	252		T3	7159
valid_sources[0x3b]	439173	1		T1	24		T2	222		T3	7119
valid_sources[0x3c]	433781	1		T1	46		T2	338		T3	7235
valid_sources[0x3d]	440563	1		T1	28		T2	219		T3	7026
valid_sources[0x3e]	441892	1		T1	48		T2	261		T3	7482
valid_sources[0x3f]	434614	1		T1	34		T2	250		T3	7474
valid_sources[0x40]	447480	1		T1	36		T2	226		T3	7537
valid_sources[0x41]	439546	1		T1	56		T2	210		T3	7804
valid_sources[0x42]	451110	1		T1	31		T2	223		T3	6820
valid_sources[0x43]	4650960	1		T1	43		T2	180		T3	7151
valid_sources[0x44]	438495	1		T1	49		T2	223		T3	6917
valid_sources[0x45]	440349	1		T1	30		T2	303		T3	7977
valid_sources[0x46]	577832	1		T1	32		T2	227		T3	7760
valid_sources[0x47]	490271	1		T1	36		T2	283		T3	7278
valid_sources[0x48]	440203	1		T1	52		T2	233		T3	7251
valid_sources[0x49]	438843	1		T1	32		T2	271		T3	7190
valid_sources[0x4a]	438219	1		T1	17		T2	253		T3	7162
valid_sources[0x4b]	437545	1		T1	48		T2	372		T3	7332
valid_sources[0x4c]	442617	1		T1	31		T2	154		T3	7015
valid_sources[0x4d]	437728	1		T1	29		T2	248		T3	7264
valid_sources[0x4e]	437929	1		T1	28		T2	191		T3	7280
valid_sources[0x4f]	440190	1		T1	21		T2	189		T3	7001
valid_sources[0x50]	436208	1		T1	40		T2	245		T3	7256
valid_sources[0x51]	3943145	1		T1	47		T2	257		T3	7478
valid_sources[0x52]	2104653	1		T1	39		T2	162		T3	7097
valid_sources[0x53]	1010885	1		T1	17		T2	350		T3	6894
valid_sources[0x54]	459239	1		T1	47		T2	328		T3	6943
valid_sources[0x55]	442302	1		T1	42		T2	182		T3	7092
valid_sources[0x56]	441009	1		T1	29		T2	225		T3	7874
valid_sources[0x57]	441454	1		T1	35		T2	186		T3	7142
valid_sources[0x58]	453030	1		T1	42		T2	183		T3	6943
valid_sources[0x59]	442626	1		T1	32		T2	239		T3	7042
valid_sources[0x5a]	437419	1		T1	29		T2	135		T3	7234
valid_sources[0x5b]	592113	1		T1	34		T2	226		T3	7590
valid_sources[0x5c]	967925	1		T1	17		T2	195		T3	7158
valid_sources[0x5d]	443532	1		T1	37		T2	152		T3	7481
valid_sources[0x5e]	444926	1		T1	55		T2	231		T3	7252
valid_sources[0x5f]	438337	1		T1	27		T2	175		T3	7615
valid_sources[0x60]	482933	1		T1	20		T2	318		T3	7508
valid_sources[0x61]	510200	1		T1	29		T2	228		T3	7426
valid_sources[0x62]	435332	1		T1	34		T2	226		T3	7290
valid_sources[0x63]	437490	1		T1	60		T2	238		T3	7477
valid_sources[0x64]	1101160	1		T1	31		T2	254		T3	7269
valid_sources[0x65]	745202	1		T1	46		T2	241		T3	7802
valid_sources[0x66]	439592	1		T1	21		T2	223		T3	7019
valid_sources[0x67]	435215	1		T1	33		T2	237		T3	7242
valid_sources[0x68]	439878	1		T1	44		T2	235		T3	7359
valid_sources[0x69]	440223	1		T1	22		T2	300		T3	6986
valid_sources[0x6a]	1073011	1		T1	26		T2	284		T3	7163
valid_sources[0x6b]	456995	1		T1	25		T2	213		T3	7357
valid_sources[0x6c]	497549	1		T1	26		T2	257		T3	6977
valid_sources[0x6d]	438698	1		T1	35		T2	197		T3	6696
valid_sources[0x6e]	500038	1		T1	37		T2	189		T3	7031
valid_sources[0x6f]	438109	1		T1	51		T2	240		T3	7714
valid_sources[0x70]	440357	1		T1	22		T2	268		T3	7214
valid_sources[0x71]	506900	1		T1	31		T2	211		T3	7271
valid_sources[0x72]	440641	1		T1	46		T2	191		T3	7036
valid_sources[0x73]	439762	1		T1	26		T2	255		T3	7038
valid_sources[0x74]	443249	1		T1	40		T2	257		T3	7392
valid_sources[0x75]	435083	1		T1	25		T2	259		T3	7223
valid_sources[0x76]	691738	1		T1	20		T2	179		T3	7067
valid_sources[0x77]	1549706	1		T1	30		T2	264		T3	7340
valid_sources[0x78]	436207	1		T1	34		T2	192		T3	7180
valid_sources[0x79]	441754	1		T1	32		T2	158		T3	7616
valid_sources[0x7a]	1432969	1		T1	61		T2	268		T3	7103
valid_sources[0x7b]	438701	1		T1	24		T2	192		T3	7706
valid_sources[0x7c]	438131	1		T1	54		T2	248		T3	7295
valid_sources[0x7d]	440062	1		T1	51		T2	283		T3	7596
valid_sources[0x7e]	442635	1		T1	28		T2	210		T3	6845
valid_sources[0x7f]	438397	1		T1	36		T2	238		T3	7418
valid_sources[0x80]	445296	1		T1	40		T2	213		T3	7031

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71964074

1

T1

4613

T2

30140

T3

928538

values[0x0]

all_enables

biggest_size

473008

1

T1

1

T2

20

T3

18

values[0x1]

all_enables

biggest_size

469414

1

T1

5

T2

11

T3

22