Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1628373	0	0
cfg0_rd_A	2147483647	4258	0	0
compare_lower0_0_rd_A	2147483647	4108	0	0
compare_upper0_0_rd_A	2147483647	3806	0	0
ctrl_rd_A	2147483647	3641	0	0
intr_enable0_rd_A	2147483647	5342	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1628373	0	0
T4	114625	46256	0	0
T5	109765	0	0	0
T6	144419	0	0	0
T7	15546	0	0	0
T8	113398	0	0	0
T9	659406	0	0	0
T10	243679	0	0	0
T11	0	90369	0	0
T12	0	97263	0	0
T18	0	205134	0	0
T35	0	158898	0	0
T36	0	125852	0	0
T37	0	99888	0	0
T38	0	53129	0	0
T39	0	94792	0	0
T40	0	32388	0	0
T41	193436	0	0	0
T42	322135	0	0	0
T43	656151	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4258	0	0
T11	352540	937	0	0
T38	0	279	0	0
T40	0	354	0	0
T44	0	957	0	0
T45	0	14	0	0
T46	0	4	0	0
T47	0	14	0	0
T48	0	144	0	0
T49	0	11	0	0
T50	0	17	0	0
T51	423296	0	0	0
T52	620489	0	0	0
T53	774397	0	0	0
T54	122709	0	0	0
T55	444755	0	0	0
T56	426913	0	0	0
T57	252421	0	0	0
T58	682185	0	0	0
T59	181031	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4108	0	0
T11	352540	970	0	0
T38	0	374	0	0
T40	0	383	0	0
T44	0	1032	0	0
T45	0	10	0	0
T46	0	8	0	0
T47	0	9	0	0
T48	0	119	0	0
T49	0	6	0	0
T50	0	6	0	0
T51	423296	0	0	0
T52	620489	0	0	0
T53	774397	0	0	0
T54	122709	0	0	0
T55	444755	0	0	0
T56	426913	0	0	0
T57	252421	0	0	0
T58	682185	0	0	0
T59	181031	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3806	0	0
T11	352540	937	0	0
T38	0	299	0	0
T40	0	303	0	0
T44	0	875	0	0
T45	0	15	0	0
T46	0	16	0	0
T47	0	6	0	0
T48	0	119	0	0
T49	0	4	0	0
T50	0	20	0	0
T51	423296	0	0	0
T52	620489	0	0	0
T53	774397	0	0	0
T54	122709	0	0	0
T55	444755	0	0	0
T56	426913	0	0	0
T57	252421	0	0	0
T58	682185	0	0	0
T59	181031	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3641	0	0
T11	352540	851	0	0
T38	0	297	0	0
T40	0	306	0	0
T44	0	894	0	0
T45	0	14	0	0
T46	0	8	0	0
T47	0	7	0	0
T48	0	127	0	0
T49	0	6	0	0
T50	0	8	0	0
T51	423296	0	0	0
T52	620489	0	0	0
T53	774397	0	0	0
T54	122709	0	0	0
T55	444755	0	0	0
T56	426913	0	0	0
T57	252421	0	0	0
T58	682185	0	0	0
T59	181031	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5342	0	0
T11	352540	1108	0	0
T34	0	66	0	0
T38	0	350	0	0
T40	0	490	0	0
T51	423296	0	0	0
T52	620489	0	0	0
T53	774397	0	0	0
T54	122709	0	0	0
T55	444755	0	0	0
T56	426913	0	0	0
T57	252421	0	0	0
T58	682185	0	0	0
T59	181031	0	0	0
T60	0	47	0	0
T61	0	46	0	0
T62	0	70	0	0
T63	0	28	0	0
T64	0	161	0	0
T65	0	41	0	0