Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2383737	0	0
cfg0_rd_A	2147483647	8673	0	0
compare_lower0_0_rd_A	2147483647	9472	0	0
compare_upper0_0_rd_A	2147483647	8190	0	0
ctrl_rd_A	2147483647	8130	0	0
intr_enable0_rd_A	2147483647	10342	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2383737	0	0
T13	550929	150480	0	0
T14	0	49853	0	0
T15	0	198064	0	0
T34	0	104250	0	0
T35	0	83037	0	0
T36	0	114501	0	0
T37	0	112180	0	0
T38	0	134127	0	0
T39	0	87216	0	0
T40	0	21174	0	0
T41	128558	0	0	0
T42	381129	0	0	0
T43	118435	0	0	0
T44	600805	0	0	0
T45	121781	0	0	0
T46	642367	0	0	0
T47	105942	0	0	0
T48	713644	0	0	0
T49	450532	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8673	0	0
T13	550929	860	0	0
T15	0	2073	0	0
T35	0	820	0	0
T37	0	1067	0	0
T38	0	1414	0	0
T39	0	971	0	0
T41	128558	0	0	0
T42	381129	0	0	0
T43	118435	0	0	0
T44	600805	0	0	0
T45	121781	0	0	0
T46	642367	0	0	0
T47	105942	0	0	0
T48	713644	0	0	0
T49	450532	0	0	0
T50	0	9	0	0
T51	0	18	0	0
T52	0	29	0	0
T53	0	53	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9472	0	0
T13	550929	961	0	0
T15	0	2293	0	0
T35	0	1023	0	0
T37	0	1458	0	0
T38	0	1359	0	0
T39	0	1078	0	0
T41	128558	0	0	0
T42	381129	0	0	0
T43	118435	0	0	0
T44	600805	0	0	0
T45	121781	0	0	0
T46	642367	0	0	0
T47	105942	0	0	0
T48	713644	0	0	0
T49	450532	0	0	0
T50	0	6	0	0
T51	0	5	0	0
T52	0	40	0	0
T54	0	1	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8190	0	0
T13	550929	739	0	0
T15	0	1890	0	0
T35	0	940	0	0
T37	0	1169	0	0
T38	0	1327	0	0
T39	0	814	0	0
T41	128558	0	0	0
T42	381129	0	0	0
T43	118435	0	0	0
T44	600805	0	0	0
T45	121781	0	0	0
T46	642367	0	0	0
T47	105942	0	0	0
T48	713644	0	0	0
T49	450532	0	0	0
T50	0	6	0	0
T51	0	7	0	0
T52	0	29	0	0
T54	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8130	0	0
T13	550929	757	0	0
T15	0	1766	0	0
T35	0	838	0	0
T37	0	1068	0	0
T38	0	1363	0	0
T39	0	951	0	0
T41	128558	0	0	0
T42	381129	0	0	0
T43	118435	0	0	0
T44	600805	0	0	0
T45	121781	0	0	0
T46	642367	0	0	0
T47	105942	0	0	0
T48	713644	0	0	0
T49	450532	0	0	0
T51	0	3	0	0
T52	0	13	0	0
T53	0	69	0	0
T54	0	1	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10342	0	0
T12	262785	56	0	0
T13	550929	845	0	0
T15	0	2267	0	0
T35	0	1029	0	0
T37	0	1420	0	0
T38	0	1595	0	0
T41	128558	0	0	0
T55	0	8	0	0
T56	0	94	0	0
T57	0	50	0	0
T58	0	24	0	0
T59	209194	0	0	0
T60	131249	0	0	0
T61	168402	0	0	0
T62	383600	0	0	0
T63	268135	0	0	0
T64	345493	0	0	0
T65	822357	0	0	0