Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1216715	0	0
cfg0_rd_A	2147483647	5672	0	0
compare_lower0_0_rd_A	2147483647	6101	0	0
compare_upper0_0_rd_A	2147483647	5173	0	0
ctrl_rd_A	2147483647	5310	0	0
intr_enable0_rd_A	2147483647	6901	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1216715	0	0
T12	828472	25708	0	0
T13	149139	346527	0	0
T14	0	393738	0	0
T26	105433	0	0	0
T27	115937	0	0	0
T32	0	76	0	0
T36	0	101084	0	0
T37	0	75850	0	0
T38	0	42034	0	0
T39	0	69913	0	0
T40	0	23943	0	0
T41	0	125004	0	0
T42	870609	0	0	0
T43	166164	0	0	0
T44	105863	0	0	0
T45	587393	0	0	0
T46	728559	0	0	0
T47	226623	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5672	0	0
T13	149139	2010	0	0
T14	104641	0	0	0
T16	4976	0	0	0
T36	0	1152	0	0
T38	0	354	0	0
T39	0	399	0	0
T40	0	292	0	0
T47	226623	0	0	0
T48	0	8	0	0
T49	0	14	0	0
T50	0	6	0	0
T51	0	20	0	0
T52	0	16	0	0
T53	648843	0	0	0
T54	229109	0	0	0
T55	661222	0	0	0
T56	513228	0	0	0
T57	227130	0	0	0
T58	734029	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6101	0	0
T13	149139	2202	0	0
T14	104641	0	0	0
T16	4976	0	0	0
T36	0	1306	0	0
T38	0	406	0	0
T39	0	424	0	0
T40	0	255	0	0
T47	226623	0	0	0
T48	0	12	0	0
T49	0	11	0	0
T50	0	13	0	0
T51	0	20	0	0
T53	648843	0	0	0
T54	229109	0	0	0
T55	661222	0	0	0
T56	513228	0	0	0
T57	227130	0	0	0
T58	734029	0	0	0
T59	0	10	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5173	0	0
T13	149139	1705	0	0
T14	104641	0	0	0
T16	4976	0	0	0
T36	0	1022	0	0
T38	0	441	0	0
T39	0	309	0	0
T40	0	216	0	0
T47	226623	0	0	0
T48	0	3	0	0
T49	0	11	0	0
T50	0	4	0	0
T51	0	18	0	0
T53	648843	0	0	0
T54	229109	0	0	0
T55	661222	0	0	0
T56	513228	0	0	0
T57	227130	0	0	0
T58	734029	0	0	0
T59	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5310	0	0
T13	149139	1757	0	0
T14	104641	0	0	0
T16	4976	0	0	0
T36	0	1215	0	0
T38	0	368	0	0
T39	0	306	0	0
T40	0	286	0	0
T47	226623	0	0	0
T48	0	4	0	0
T49	0	12	0	0
T50	0	1	0	0
T51	0	41	0	0
T53	648843	0	0	0
T54	229109	0	0	0
T55	661222	0	0	0
T56	513228	0	0	0
T57	227130	0	0	0
T58	734029	0	0	0
T59	0	7	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6901	0	0
T13	149139	2165	0	0
T14	104641	0	0	0
T16	4976	0	0	0
T36	0	1349	0	0
T47	226623	0	0	0
T53	648843	0	0	0
T54	229109	0	0	0
T55	661222	0	0	0
T56	513228	0	0	0
T57	227130	0	0	0
T58	734029	0	0	0
T60	0	56	0	0
T61	0	93	0	0
T62	0	16	0	0
T63	0	24	0	0
T64	0	6	0	0
T65	0	31	0	0
T66	0	32	0	0
T67	0	46	0	0