Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2359506	0	0
cfg0_rd_A	2147483647	5023	0	0
compare_lower0_0_rd_A	2147483647	4862	0	0
compare_upper0_0_rd_A	2147483647	4459	0	0
ctrl_rd_A	2147483647	4382	0	0
intr_enable0_rd_A	2147483647	6029	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2359506	0	0
T4	973232	147623	0	0
T5	350720	0	0	0
T6	258238	0	0	0
T7	303701	0	0	0
T8	636271	0	0	0
T9	278089	0	0	0
T10	106625	0	0	0
T11	0	137618	0	0
T12	0	53806	0	0
T31	0	250515	0	0
T32	0	62225	0	0
T33	0	164597	0	0
T34	0	254969	0	0
T35	0	227096	0	0
T36	0	88331	0	0
T37	0	188219	0	0
T38	134259	0	0	0
T39	809109	0	0	0
T40	764020	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5023	0	0
T35	872732	2502	0	0
T36	206410	0	0	0
T37	0	1031	0	0
T41	0	9	0	0
T42	0	19	0	0
T43	0	3	0	0
T44	0	42	0	0
T45	0	9	0	0
T46	0	36	0	0
T47	0	79	0	0
T48	0	195	0	0
T49	937483	0	0	0
T50	125765	0	0	0
T51	384111	0	0	0
T52	236880	0	0	0
T53	101490	0	0	0
T54	471403	0	0	0
T55	115158	0	0	0
T56	506374	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4862	0	0
T35	872732	2549	0	0
T36	206410	0	0	0
T37	0	1174	0	0
T41	0	12	0	0
T42	0	14	0	0
T43	0	2	0	0
T44	0	36	0	0
T46	0	32	0	0
T47	0	81	0	0
T48	0	126	0	0
T49	937483	0	0	0
T50	125765	0	0	0
T51	384111	0	0	0
T52	236880	0	0	0
T53	101490	0	0	0
T54	471403	0	0	0
T55	115158	0	0	0
T56	506374	0	0	0
T57	0	8	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4459	0	0
T35	872732	2349	0	0
T36	206410	0	0	0
T37	0	1006	0	0
T41	0	8	0	0
T42	0	17	0	0
T44	0	32	0	0
T45	0	6	0	0
T46	0	26	0	0
T47	0	78	0	0
T48	0	135	0	0
T49	937483	0	0	0
T50	125765	0	0	0
T51	384111	0	0	0
T52	236880	0	0	0
T53	101490	0	0	0
T54	471403	0	0	0
T55	115158	0	0	0
T56	506374	0	0	0
T58	0	89	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4382	0	0
T35	872732	2348	0	0
T36	206410	0	0	0
T37	0	936	0	0
T41	0	9	0	0
T42	0	3	0	0
T44	0	38	0	0
T45	0	5	0	0
T46	0	54	0	0
T47	0	67	0	0
T48	0	118	0	0
T49	937483	0	0	0
T50	125765	0	0	0
T51	384111	0	0	0
T52	236880	0	0	0
T53	101490	0	0	0
T54	471403	0	0	0
T55	115158	0	0	0
T56	506374	0	0	0
T58	0	65	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6029	0	0
T1	174644	67	0	0
T2	503441	0	0	0
T3	7953	0	0	0
T4	973232	0	0	0
T5	350720	0	0	0
T6	258238	0	0	0
T7	303701	0	0	0
T8	636271	56	0	0
T9	278089	0	0	0
T10	106625	0	0	0
T59	0	32	0	0
T60	0	19	0	0
T61	0	61	0	0
T62	0	16	0	0
T63	0	11	0	0
T64	0	24	0	0
T65	0	53	0	0
T66	0	39	0	0