Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1922618	0	0
cfg0_rd_A	2147483647	5613	0	0
compare_lower0_0_rd_A	2147483647	6001	0	0
compare_upper0_0_rd_A	2147483647	5324	0	0
ctrl_rd_A	2147483647	5281	0	0
intr_enable0_rd_A	2147483647	7184	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1922618	0	0
T14	238545	71867	0	0
T15	0	243940	0	0
T16	0	164813	0	0
T36	0	188586	0	0
T37	0	40826	0	0
T38	0	60195	0	0
T39	0	241159	0	0
T40	0	56167	0	0
T41	0	218457	0	0
T42	0	72310	0	0
T43	727586	0	0	0
T44	437326	0	0	0
T45	530914	0	0	0
T46	124949	0	0	0
T47	143384	0	0	0
T48	310570	0	0	0
T49	386205	0	0	0
T50	196009	0	0	0
T51	102660	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5613	0	0
T15	109085	2408	0	0
T16	396799	0	0	0
T34	0	664	0	0
T36	445334	0	0	0
T42	0	355	0	0
T52	0	124	0	0
T53	0	15	0	0
T54	0	6	0	0
T55	0	51	0	0
T56	0	167	0	0
T57	0	2	0	0
T58	0	5	0	0
T59	676540	0	0	0
T60	395393	0	0	0
T61	16744	0	0	0
T62	277566	0	0	0
T63	420421	0	0	0
T64	140760	0	0	0
T65	895508	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6001	0	0
T15	109085	2747	0	0
T16	396799	0	0	0
T34	0	643	0	0
T36	445334	0	0	0
T42	0	511	0	0
T52	0	156	0	0
T53	0	10	0	0
T54	0	2	0	0
T55	0	41	0	0
T56	0	128	0	0
T57	0	6	0	0
T59	676540	0	0	0
T60	395393	0	0	0
T61	16744	0	0	0
T62	277566	0	0	0
T63	420421	0	0	0
T64	140760	0	0	0
T65	895508	0	0	0
T66	0	8	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5324	0	0
T15	109085	2376	0	0
T16	396799	0	0	0
T34	0	617	0	0
T36	445334	0	0	0
T42	0	375	0	0
T52	0	98	0	0
T53	0	9	0	0
T54	0	7	0	0
T55	0	31	0	0
T56	0	108	0	0
T57	0	10	0	0
T58	0	7	0	0
T59	676540	0	0	0
T60	395393	0	0	0
T61	16744	0	0	0
T62	277566	0	0	0
T63	420421	0	0	0
T64	140760	0	0	0
T65	895508	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5281	0	0
T15	109085	2343	0	0
T16	396799	0	0	0
T34	0	594	0	0
T36	445334	0	0	0
T42	0	295	0	0
T52	0	118	0	0
T53	0	6	0	0
T54	0	3	0	0
T55	0	34	0	0
T56	0	102	0	0
T57	0	6	0	0
T59	676540	0	0	0
T60	395393	0	0	0
T61	16744	0	0	0
T62	277566	0	0	0
T63	420421	0	0	0
T64	140760	0	0	0
T65	895508	0	0	0
T67	0	10	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7184	0	0
T15	109085	2964	0	0
T16	396799	0	0	0
T36	445334	0	0	0
T59	676540	0	0	0
T60	395393	0	0	0
T61	16744	0	0	0
T62	277566	0	0	0
T63	420421	0	0	0
T64	140760	0	0	0
T65	895508	0	0	0
T68	0	31	0	0
T69	0	47	0	0
T70	0	38	0	0
T71	0	39	0	0
T72	0	16	0	0
T73	0	43	0	0
T74	0	110	0	0
T75	0	20	0	0
T76	0	56	0	0