Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59646162	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	61131245	1		T1	279435		T2	68918		T3	14085

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	119491721	1		T1	81169		T2	137982		T3	28205
values[0x0]	611755	1		T1	104562		T2	14		T3	14
values[0x1]	673931	1		T1	115096		T2	17		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47636946	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	73140461	1		T1	289965		T2	82946		T3	16949

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	320102	1		T1	952		T3	121		T5	955
valid_sources[0x01]	321438	1		T1	1196		T3	105		T5	913
valid_sources[0x02]	318242	1		T1	830		T3	134		T5	888
valid_sources[0x03]	513542	1		T1	900		T3	193		T5	948
valid_sources[0x04]	523913	1		T1	1405		T3	47		T5	948
valid_sources[0x05]	318310	1		T1	2202		T3	113		T5	918
valid_sources[0x06]	332403	1		T1	1296		T3	109		T5	955
valid_sources[0x07]	317547	1		T1	1306		T3	45		T5	964
valid_sources[0x08]	317526	1		T1	788		T3	76		T5	965
valid_sources[0x09]	321934	1		T1	1056		T3	118		T5	903
valid_sources[0x0a]	321054	1		T1	890		T3	110		T5	935
valid_sources[0x0b]	395943	1		T1	1254		T3	162		T5	967
valid_sources[0x0c]	538791	1		T1	1100		T3	141		T5	916
valid_sources[0x0d]	322120	1		T1	1370		T3	103		T5	965
valid_sources[0x0e]	319416	1		T1	1148		T3	114		T5	958
valid_sources[0x0f]	317247	1		T1	1361		T3	173		T5	979
valid_sources[0x10]	319513	1		T1	1341		T3	88		T5	939
valid_sources[0x11]	319560	1		T1	1204		T3	104		T5	981
valid_sources[0x12]	318316	1		T1	1178		T3	109		T5	999
valid_sources[0x13]	1350374	1		T1	1840		T3	149		T5	936
valid_sources[0x14]	327577	1		T1	1080		T3	50		T5	893
valid_sources[0x15]	316935	1		T1	1209		T3	142		T5	962
valid_sources[0x16]	316527	1		T1	1069		T3	73		T5	900
valid_sources[0x17]	342638	1		T1	1304		T3	50		T5	928
valid_sources[0x18]	315431	1		T1	911		T3	97		T5	862
valid_sources[0x19]	322530	1		T1	1075		T3	169		T5	950
valid_sources[0x1a]	318172	1		T1	1555		T3	120		T5	965
valid_sources[0x1b]	317659	1		T1	1466		T3	89		T5	1011
valid_sources[0x1c]	321229	1		T1	1072		T3	196		T5	945
valid_sources[0x1d]	319148	1		T1	784		T3	189		T5	915
valid_sources[0x1e]	364756	1		T1	1523		T3	224		T5	952
valid_sources[0x1f]	319780	1		T1	1170		T3	60		T5	946
valid_sources[0x20]	346057	1		T1	1501		T3	61		T5	964
valid_sources[0x21]	362077	1		T1	923		T3	119		T5	939
valid_sources[0x22]	322507	1		T1	1277		T3	104		T5	996
valid_sources[0x23]	319797	1		T1	1158		T3	72		T5	951
valid_sources[0x24]	3310401	1		T1	1136		T3	61		T5	957
valid_sources[0x25]	319108	1		T1	1115		T3	85		T5	979
valid_sources[0x26]	321269	1		T1	729		T3	112		T5	961
valid_sources[0x27]	318679	1		T1	1316		T3	125		T5	939
valid_sources[0x28]	321484	1		T1	1607		T3	89		T5	958
valid_sources[0x29]	329155	1		T1	1243		T3	19		T5	964
valid_sources[0x2a]	635950	1		T1	559		T3	86		T5	957
valid_sources[0x2b]	319316	1		T1	847		T3	175		T5	974
valid_sources[0x2c]	1235822	1		T1	2060		T3	59		T5	960
valid_sources[0x2d]	320242	1		T1	1052		T3	134		T5	956
valid_sources[0x2e]	321369	1		T1	1269		T3	103		T5	965
valid_sources[0x2f]	360540	1		T1	893		T3	66		T5	912
valid_sources[0x30]	895206	1		T1	1228		T3	128		T5	903
valid_sources[0x31]	331631	1		T1	1089		T3	94		T5	931
valid_sources[0x32]	402731	1		T1	1284		T3	34		T5	950
valid_sources[0x33]	318931	1		T1	1158		T3	112		T5	939
valid_sources[0x34]	2633482	1		T1	1137		T3	91		T5	919
valid_sources[0x35]	318371	1		T1	1366		T3	85		T5	946
valid_sources[0x36]	319057	1		T1	1368		T3	97		T5	965
valid_sources[0x37]	321589	1		T1	1579		T3	85		T5	889
valid_sources[0x38]	317633	1		T1	1002		T3	61		T5	970
valid_sources[0x39]	322192	1		T1	1380		T3	84		T5	945
valid_sources[0x3a]	318398	1		T1	1215		T3	133		T5	977
valid_sources[0x3b]	322713	1		T1	1553		T3	47		T5	907
valid_sources[0x3c]	1389317	1		T1	1171		T3	97		T5	883
valid_sources[0x3d]	317959	1		T1	1159		T3	148		T5	932
valid_sources[0x3e]	1003321	1		T1	897		T3	135		T5	886
valid_sources[0x3f]	328990	1		T1	1243		T3	128		T5	1014
valid_sources[0x40]	736079	1		T1	1091		T3	98		T5	977
valid_sources[0x41]	318032	1		T1	1049		T3	91		T5	1026
valid_sources[0x42]	319480	1		T1	1314		T3	96		T5	1044
valid_sources[0x43]	318561	1		T1	1205		T3	152		T5	903
valid_sources[0x44]	336600	1		T1	787		T3	62		T5	946
valid_sources[0x45]	320121	1		T1	1246		T3	86		T5	984
valid_sources[0x46]	320174	1		T1	852		T3	153		T5	963
valid_sources[0x47]	968328	1		T1	1075		T3	206		T5	963
valid_sources[0x48]	577882	1		T1	772		T3	66		T5	903
valid_sources[0x49]	320668	1		T1	1210		T3	86		T5	907
valid_sources[0x4a]	322347	1		T1	1238		T3	156		T5	973
valid_sources[0x4b]	336608	1		T1	1235		T3	127		T5	999
valid_sources[0x4c]	906624	1		T1	1229		T3	59		T5	981
valid_sources[0x4d]	319499	1		T1	1130		T3	141		T5	959
valid_sources[0x4e]	319720	1		T1	938		T3	200		T5	976
valid_sources[0x4f]	316781	1		T1	567		T3	183		T5	921
valid_sources[0x50]	318528	1		T1	770		T3	143		T5	957
valid_sources[0x51]	319275	1		T1	859		T3	45		T5	969
valid_sources[0x52]	322556	1		T1	1208		T3	79		T5	976
valid_sources[0x53]	317949	1		T1	925		T3	43		T5	1000
valid_sources[0x54]	327041	1		T1	776		T3	125		T5	932
valid_sources[0x55]	320329	1		T1	1719		T3	88		T5	999
valid_sources[0x56]	339929	1		T1	1595		T3	68		T5	926
valid_sources[0x57]	375375	1		T1	1054		T3	184		T5	956
valid_sources[0x58]	2289611	1		T1	1162		T3	114		T5	943
valid_sources[0x59]	416711	1		T1	1269		T3	101		T5	933
valid_sources[0x5a]	347754	1		T1	1378		T3	98		T5	969
valid_sources[0x5b]	355869	1		T1	1449		T3	113		T5	957
valid_sources[0x5c]	316285	1		T1	1519		T3	36		T5	988
valid_sources[0x5d]	3069741	1		T1	859		T3	115		T5	922
valid_sources[0x5e]	320626	1		T1	1450		T3	149		T5	999
valid_sources[0x5f]	317909	1		T1	1301		T3	116		T5	935
valid_sources[0x60]	321567	1		T1	989		T3	59		T5	948
valid_sources[0x61]	320852	1		T1	1655		T3	100		T5	987
valid_sources[0x62]	318401	1		T1	750		T3	66		T5	976
valid_sources[0x63]	319515	1		T1	1143		T3	120		T5	974
valid_sources[0x64]	1295958	1		T1	1161		T3	122		T5	957
valid_sources[0x65]	3838494	1		T1	1286		T3	191		T5	865
valid_sources[0x66]	328323	1		T1	1265		T3	124		T5	897
valid_sources[0x67]	318184	1		T1	1662		T3	61		T5	964
valid_sources[0x68]	320500	1		T1	1166		T3	87		T5	933
valid_sources[0x69]	318386	1		T1	1335		T3	117		T5	903
valid_sources[0x6a]	316587	1		T1	840		T3	89		T5	933
valid_sources[0x6b]	509593	1		T1	1401		T3	101		T5	893
valid_sources[0x6c]	3036184	1		T1	1467		T3	106		T5	929
valid_sources[0x6d]	320306	1		T1	1836		T3	177		T5	978
valid_sources[0x6e]	320954	1		T1	1128		T3	64		T5	922
valid_sources[0x6f]	321376	1		T1	1732		T3	66		T5	1012
valid_sources[0x70]	350198	1		T1	1285		T3	94		T5	874
valid_sources[0x71]	319635	1		T1	1087		T3	63		T5	1001
valid_sources[0x72]	319752	1		T1	658		T3	132		T5	995
valid_sources[0x73]	318354	1		T1	1390		T3	167		T5	929
valid_sources[0x74]	319312	1		T1	673		T3	214		T5	958
valid_sources[0x75]	1602244	1		T1	889		T3	104		T5	905
valid_sources[0x76]	319315	1		T1	1734		T3	192		T5	947
valid_sources[0x77]	319855	1		T1	1248		T3	163		T5	948
valid_sources[0x78]	1017816	1		T1	1375		T3	79		T5	953
valid_sources[0x79]	318294	1		T1	877		T3	56		T5	955
valid_sources[0x7a]	383352	1		T1	1043		T3	53		T5	1034
valid_sources[0x7b]	318761	1		T1	1011		T3	161		T5	918
valid_sources[0x7c]	314727	1		T1	998		T3	88		T5	959
valid_sources[0x7d]	350083	1		T1	1051		T3	99		T5	965
valid_sources[0x7e]	321460	1		T1	1377		T3	146		T5	916
valid_sources[0x7f]	530539	1		T1	1018		T3	132		T5	929
valid_sources[0x80]	727200	1		T1	1143		T3	79		T5	931

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59932800

1

T1

73074

T2

68899

T3

14057

values[0x0]

all_enables

biggest_size

600766

1

T1

103383

T2

9

T3

11

values[0x1]

all_enables

biggest_size

597679

1

T1

102978

T2

10

T3

17