Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

19 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rv_timer-0-prescale-0 100.00 1 100 1 64 64
rv_timer-0-prescale-1 100.00 1 100 1 64 64
rv_timer-0-prescale-10 100.00 1 100 1 64 64
rv_timer-0-prescale-11 100.00 1 100 1 64 64
rv_timer-0-prescale-2 100.00 1 100 1 64 64
rv_timer-0-prescale-3 100.00 1 100 1 64 64
rv_timer-0-prescale-4 100.00 1 100 1 64 64
rv_timer-0-prescale-5 100.00 1 100 1 64 64
rv_timer-0-prescale-6 100.00 1 100 1 64 64
rv_timer-0-prescale-7 100.00 1 100 1 64 64
rv_timer-0-prescale-8 100.00 1 100 1 64 64
rv_timer-0-prescale-9 100.00 1 100 1 64 64
rv_timer_sticky_intr_pin0 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max 100.00 1 100 1 64 64




Group Instance : rv_timer-0-prescale-0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-10
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-10

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-10
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-11
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-11

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-11
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-5
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-6
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer-0-prescale-9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer-0-prescale-9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer-0-prescale-9
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : rv_timer_sticky_intr_pin0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer_sticky_intr_pin0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance rv_timer_sticky_intr_pin0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 0 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::PutFullData_mask_not_match_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_mask
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::addr_not_align_size
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::invalid_a_opcode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::mask_not_in_enabled_lanes
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2



Group Instance : uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::size_over_max
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 213 1 T4 1 T5 1 T116 2
rising 184 1 T4 1 T5 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 623 1 T1 1 T4 2 T5 1
auto[1] 579 1 T2 3 T3 4 T4 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 225 1 T3 1 T5 1 T9 1
rising 231 1 T2 1 T3 1 T5 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 578 1 T2 2 T3 2 T4 3
auto[1] 624 1 T1 1 T2 1 T3 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 219 1 T2 1 T5 2 T9 1
rising 207 1 T3 1 T5 1 T10 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 587 1 T2 2 T3 3 T5 2
auto[1] 615 1 T1 1 T2 1 T3 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 196 1 T2 1 T3 1 T4 1
rising 217 1 T2 1 T3 1 T5 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 589 1 T1 1 T2 2 T3 3
auto[1] 613 1 T2 1 T3 1 T4 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 223 1 T2 1 T3 2 T5 2
rising 216 1 T3 1 T4 1 T5 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 625 1 T1 1 T2 2 T3 2
auto[1] 577 1 T2 1 T3 2 T4 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 222 1 T4 1 T5 1 T116 2
rising 237 1 T5 2 T6 1 T116 2



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 598 1 T3 4 T4 2 T5 2
auto[1] 604 1 T1 1 T2 3 T4 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 233 1 T2 1 T4 1 T5 1
rising 236 1 T3 1 T4 1 T5 2



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 596 1 T1 1 T2 2 T3 1
auto[1] 606 1 T2 1 T3 3 T4 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 208 1 T116 2 T11 4 T147 1
rising 249 1 T5 1 T6 1 T10 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 602 1 T1 1 T2 3 T4 3
auto[1] 600 1 T3 4 T5 4 T6 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 223 1 T2 1 T3 1 T5 1
rising 227 1 T2 1 T3 1 T5 2



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 582 1 T1 1 T2 2 T3 1
auto[1] 620 1 T2 1 T3 3 T5 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 237 1 T2 1 T4 1 T5 1
rising 221 1 T3 1 T5 1 T6 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 565 1 T1 1 T2 2 T3 2
auto[1] 637 1 T2 1 T3 2 T4 1


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 204 1 T3 1 T5 1 T9 1
rising 234 1 T3 1 T116 1 T11 4



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 594 1 T1 1 T3 1 T4 3
auto[1] 608 1 T2 3 T3 3 T5 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 212 1 T2 1 T3 1 T4 1
rising 248 1 T4 1 T6 1 T9 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 570 1 T1 1 T2 2 T3 3
auto[1] 632 1 T2 1 T3 1 T4 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 69 1 T6 1 T10 1 T129 1
rising 69 1 T6 1 T10 1 T129 1



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6947 1 T1 47 T2 10 T3 14
auto[1] 105 1 T6 2 T10 1 T129 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 395333 1 T1 68242 T13 8664 T14 25279
rising 395324 1 T1 68241 T13 8664 T14 25279



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2712048 1 T1 468244 T13 57668 T14 175769
auto[1] 472116 1 T1 81418 T13 10396 T14 30137


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 762374 1 T1 131492 T13 16334 T14 49127
rising 762378 1 T1 131492 T13 16333 T14 49128



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1895691 1 T1 326796 T13 40528 T14 122144
auto[1] 1288473 1 T1 222866 T13 27536 T14 83762


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 762374 1 T1 131492 T13 16334 T14 49127
rising 762378 1 T1 131492 T13 16333 T14 49128



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1895691 1 T1 326796 T13 40528 T14 122144
auto[1] 1288473 1 T1 222866 T13 27536 T14 83762


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 777353 1 T1 134132 T13 16610 T14 50294
rising 777359 1 T1 134132 T13 16610 T14 50293



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1712429 1 T1 295071 T13 36780 T14 109708
auto[1] 1471735 1 T1 254591 T13 31284 T14 96198


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 561834 1 T1 96766 T13 11935 T14 36485
rising 561830 1 T1 96765 T13 11936 T14 36485



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2448913 1 T1 423060 T13 52445 T14 157984
auto[1] 735251 1 T1 126602 T13 15619 T14 47922


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
falling 573112 1 T1 98655 T13 12180 T14 37166
rising 573108 1 T1 98655 T13 12179 T14 37166



Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2433940 1 T1 420488 T13 52068 T14 157177
auto[1] 750224 1 T1 129174 T13 15996 T14 48729

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%