Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2095436	0	0
cfg0_rd_A	2147483647	4423	0	0
compare_lower0_0_rd_A	2147483647	4324	0	0
compare_upper0_0_rd_A	2147483647	4082	0	0
ctrl_rd_A	2147483647	4120	0	0
intr_enable0_rd_A	2147483647	5282	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095436	0	0
T1	918385	362301	0	0
T2	931935	0	0	0
T3	581318	0	0	0
T4	474040	0	0	0
T5	108874	0	0	0
T6	451218	0	0	0
T7	383101	0	0	0
T8	369924	0	0	0
T9	827658	0	0	0
T10	172148	0	0	0
T13	0	45944	0	0
T14	0	136446	0	0
T25	0	40513	0	0
T34	0	170601	0	0
T35	0	75978	0	0
T36	0	183529	0	0
T37	0	158419	0	0
T38	0	168541	0	0
T39	0	119828	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4423	0	0
T31	0	156	0	0
T36	672983	1111	0	0
T40	0	784	0	0
T41	0	347	0	0
T42	0	8	0	0
T43	0	4	0	0
T44	0	7	0	0
T45	0	83	0	0
T46	0	1	0	0
T47	0	6	0	0
T48	201300	0	0	0
T49	518524	0	0	0
T50	427973	0	0	0
T51	375873	0	0	0
T52	187631	0	0	0
T53	880857	0	0	0
T54	979353	0	0	0
T55	565965	0	0	0
T56	372493	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4324	0	0
T36	672983	1043	0	0
T40	0	943	0	0
T41	0	457	0	0
T42	0	12	0	0
T43	0	23	0	0
T44	0	7	0	0
T45	0	46	0	0
T46	0	9	0	0
T47	0	10	0	0
T48	201300	0	0	0
T49	518524	0	0	0
T50	427973	0	0	0
T51	375873	0	0	0
T52	187631	0	0	0
T53	880857	0	0	0
T54	979353	0	0	0
T55	565965	0	0	0
T56	372493	0	0	0
T57	0	6	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4082	0	0
T31	0	123	0	0
T36	672983	1019	0	0
T40	0	871	0	0
T41	0	337	0	0
T42	0	1	0	0
T43	0	48	0	0
T44	0	9	0	0
T45	0	3	0	0
T46	0	4	0	0
T48	201300	0	0	0
T49	518524	0	0	0
T50	427973	0	0	0
T51	375873	0	0	0
T52	187631	0	0	0
T53	880857	0	0	0
T54	979353	0	0	0
T55	565965	0	0	0
T56	372493	0	0	0
T58	0	17	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4120	0	0
T36	672983	1020	0	0
T40	0	719	0	0
T41	0	393	0	0
T42	0	14	0	0
T43	0	45	0	0
T44	0	9	0	0
T45	0	90	0	0
T46	0	5	0	0
T47	0	10	0	0
T48	201300	0	0	0
T49	518524	0	0	0
T50	427973	0	0	0
T51	375873	0	0	0
T52	187631	0	0	0
T53	880857	0	0	0
T54	979353	0	0	0
T55	565965	0	0	0
T56	372493	0	0	0
T57	0	7	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5282	0	0
T36	0	1252	0	0
T40	0	1002	0	0
T41	0	399	0	0
T59	632853	55	0	0
T60	0	21	0	0
T61	0	73	0	0
T62	0	56	0	0
T63	0	13	0	0
T64	0	27	0	0
T65	0	30	0	0
T66	368273	0	0	0
T67	176762	0	0	0
T68	438361	0	0	0
T69	372887	0	0	0
T70	15850	0	0	0
T71	212645	0	0	0
T72	275368	0	0	0
T73	107652	0	0	0
T74	125872	0	0	0