SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_timer_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 118279703 | 0 | T1 | 79142 | T2 | 38033 | T3 | 46576 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 118279453 | 1 | T1 | 79142 | T2 | 38033 | T3 | 46576 | |||
values[1] | 27 | 1 | T28 | 2 | T29 | 2 | T30 | 2 | |||
values[2] | 3 | 1 | T109 | 1 | T110 | 1 | T111 | 1 | |||
values[3] | 135 | 1 | T28 | 7 | T29 | 2 | T30 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 118279445 | 1 | T1 | 79142 | T2 | 38033 | T3 | 46576 | |||
values[1] | 28 | 1 | T30 | 3 | T112 | 1 | T113 | 2 | |||
values[2] | 2 | 1 | T111 | 2 | - | - | - | - | |||
values[3] | 124 | 1 | T28 | 13 | T29 | 3 | T30 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 118279323 | 1 | T1 | 79142 | T2 | 38033 | T3 | 46576 | |||
auto[TlIntgErrCmd] | 122 | 1 | T28 | 7 | T29 | 5 | T30 | 6 | |||
auto[TlIntgErrData] | 130 | 1 | T28 | 13 | T29 | 2 | T30 | 8 | |||
auto[TlIntgErrBoth] | 128 | 1 | T28 | 10 | T29 | 3 | T30 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |