Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1523092	0	0
cfg0_rd_A	2147483647	4169	0	0
compare_lower0_0_rd_A	2147483647	4813	0	0
compare_upper0_0_rd_A	2147483647	4034	0	0
ctrl_rd_A	2147483647	4195	0	0
intr_enable0_rd_A	2147483647	5290	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523092	0	0
T13	187200	56082	0	0
T14	0	165613	0	0
T15	0	100731	0	0
T34	219466	0	0	0
T35	0	151244	0	0
T36	0	89251	0	0
T37	0	418004	0	0
T38	0	68706	0	0
T39	0	40491	0	0
T40	0	144457	0	0
T41	0	73910	0	0
T42	123096	0	0	0
T43	156641	0	0	0
T44	375437	0	0	0
T45	252959	0	0	0
T46	772009	0	0	0
T47	613960	0	0	0
T48	234356	0	0	0
T49	729609	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4169	0	0
T31	0	46	0	0
T32	0	390	0	0
T35	633051	817	0	0
T36	322150	0	0	0
T40	0	1284	0	0
T41	0	410	0	0
T50	0	19	0	0
T51	0	12	0	0
T52	0	3	0	0
T53	0	11	0	0
T54	0	14	0	0
T55	371401	0	0	0
T56	249487	0	0	0
T57	721673	0	0	0
T58	127852	0	0	0
T59	545634	0	0	0
T60	343659	0	0	0
T61	141932	0	0	0
T62	155900	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4813	0	0
T31	0	44	0	0
T32	0	430	0	0
T35	633051	959	0	0
T36	322150	0	0	0
T40	0	1776	0	0
T41	0	442	0	0
T50	0	32	0	0
T52	0	17	0	0
T53	0	15	0	0
T54	0	6	0	0
T55	371401	0	0	0
T56	249487	0	0	0
T57	721673	0	0	0
T58	127852	0	0	0
T59	545634	0	0	0
T60	343659	0	0	0
T61	141932	0	0	0
T62	155900	0	0	0
T63	0	5	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4034	0	0
T31	0	50	0	0
T32	0	403	0	0
T35	633051	825	0	0
T36	322150	0	0	0
T40	0	1337	0	0
T41	0	367	0	0
T50	0	39	0	0
T52	0	5	0	0
T53	0	2	0	0
T55	371401	0	0	0
T56	249487	0	0	0
T57	721673	0	0	0
T58	127852	0	0	0
T59	545634	0	0	0
T60	343659	0	0	0
T61	141932	0	0	0
T62	155900	0	0	0
T63	0	3	0	0
T64	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4195	0	0
T31	0	50	0	0
T32	0	400	0	0
T35	633051	748	0	0
T36	322150	0	0	0
T40	0	1547	0	0
T41	0	338	0	0
T50	0	8	0	0
T52	0	18	0	0
T53	0	6	0	0
T54	0	7	0	0
T55	371401	0	0	0
T56	249487	0	0	0
T57	721673	0	0	0
T58	127852	0	0	0
T59	545634	0	0	0
T60	343659	0	0	0
T61	141932	0	0	0
T62	155900	0	0	0
T65	0	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5290	0	0
T13	187200	0	0	0
T25	919010	11	0	0
T26	112432	0	0	0
T27	115227	0	0	0
T35	0	915	0	0
T40	0	1692	0	0
T41	0	376	0	0
T66	0	26	0	0
T67	0	22	0	0
T68	0	100	0	0
T69	0	19	0	0
T70	0	106	0	0
T71	0	24	0	0
T72	934522	0	0	0
T73	584115	0	0	0
T74	924848	0	0	0
T75	195998	0	0	0
T76	341214	0	0	0
T77	158573	0	0	0