Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57472058	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	58494678	1		T1	1877		T2	22839		T3	53256

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	115080977	1		T1	3733		T2	7491		T3	26902
values[0x0]	421413	1		T1	12		T2	8353		T3	17433
values[0x1]	464346	1		T1	8		T2	9083		T3	19230

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45899172	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	70067564	1		T1	2260		T2	23709		T3	56349

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	343280	1		T2	97		T3	277		T5	73
valid_sources[0x01]	338651	1		T2	89		T3	188		T5	59
valid_sources[0x02]	337604	1		T2	109		T3	276		T5	58
valid_sources[0x03]	338483	1		T2	92		T3	410		T5	95
valid_sources[0x04]	339513	1		T2	111		T3	8		T5	99
valid_sources[0x05]	340442	1		T2	96		T3	354		T5	95
valid_sources[0x06]	343231	1		T2	88		T3	1		T5	95
valid_sources[0x07]	334648	1		T2	91		T3	301		T5	72
valid_sources[0x08]	339457	1		T2	104		T3	2		T5	124
valid_sources[0x09]	897120	1		T2	115		T3	171		T5	72
valid_sources[0x0a]	480330	1		T2	90		T3	256		T5	39
valid_sources[0x0b]	335042	1		T2	116		T3	108		T5	134
valid_sources[0x0c]	539578	1		T2	93		T5	40		T7	885
valid_sources[0x0d]	534811	1		T2	97		T3	241		T5	84
valid_sources[0x0e]	339074	1		T2	99		T5	78		T7	799
valid_sources[0x0f]	337376	1		T2	92		T3	5		T5	93
valid_sources[0x10]	1095822	1		T2	95		T3	154		T5	88
valid_sources[0x11]	365364	1		T2	117		T5	37		T7	849
valid_sources[0x12]	341088	1		T2	87		T3	330		T5	126
valid_sources[0x13]	341423	1		T2	115		T3	219		T5	98
valid_sources[0x14]	359113	1		T2	100		T3	204		T5	44
valid_sources[0x15]	348371	1		T2	112		T3	488		T5	27
valid_sources[0x16]	337265	1		T2	96		T5	75		T7	865
valid_sources[0x17]	341411	1		T2	112		T3	109		T5	87
valid_sources[0x18]	338660	1		T2	102		T3	64		T5	55
valid_sources[0x19]	340733	1		T2	122		T3	391		T5	65
valid_sources[0x1a]	340300	1		T2	104		T3	315		T5	88
valid_sources[0x1b]	339001	1		T2	88		T3	142		T5	83
valid_sources[0x1c]	336619	1		T2	97		T3	659		T5	114
valid_sources[0x1d]	350584	1		T2	81		T3	286		T5	67
valid_sources[0x1e]	337300	1		T2	92		T3	210		T5	66
valid_sources[0x1f]	335632	1		T2	108		T3	565		T5	61
valid_sources[0x20]	335979	1		T2	77		T5	46		T7	838
valid_sources[0x21]	420685	1		T2	85		T5	51		T7	854
valid_sources[0x22]	338479	1		T2	120		T3	354		T5	36
valid_sources[0x23]	337820	1		T2	100		T3	146		T5	38
valid_sources[0x24]	338121	1		T2	99		T3	301		T5	93
valid_sources[0x25]	339779	1		T2	113		T3	117		T5	119
valid_sources[0x26]	719408	1		T2	100		T3	293		T5	61
valid_sources[0x27]	387935	1		T2	72		T3	651		T5	72
valid_sources[0x28]	339261	1		T2	103		T3	69		T5	78
valid_sources[0x29]	340963	1		T2	94		T5	92		T7	851
valid_sources[0x2a]	351637	1		T2	89		T3	166		T5	93
valid_sources[0x2b]	338268	1		T2	102		T3	12		T5	31
valid_sources[0x2c]	339036	1		T2	113		T3	140		T5	52
valid_sources[0x2d]	395674	1		T2	91		T3	168		T5	35
valid_sources[0x2e]	342418	1		T2	89		T3	216		T5	70
valid_sources[0x2f]	341989	1		T2	103		T3	15		T5	20
valid_sources[0x30]	417596	1		T2	85		T3	409		T5	33
valid_sources[0x31]	342392	1		T2	97		T3	189		T5	50
valid_sources[0x32]	337666	1		T2	94		T3	337		T5	74
valid_sources[0x33]	339874	1		T2	98		T3	337		T5	52
valid_sources[0x34]	338695	1		T2	114		T5	67		T7	882
valid_sources[0x35]	338509	1		T2	111		T3	107		T5	99
valid_sources[0x36]	358521	1		T2	116		T3	13		T5	96
valid_sources[0x37]	334183	1		T2	96		T5	55		T7	807
valid_sources[0x38]	336776	1		T2	72		T5	52		T7	822
valid_sources[0x39]	348038	1		T2	100		T3	118		T5	74
valid_sources[0x3a]	340311	1		T2	90		T3	413		T5	20
valid_sources[0x3b]	337759	1		T2	96		T3	88		T5	80
valid_sources[0x3c]	337625	1		T2	108		T5	80		T7	848
valid_sources[0x3d]	339305	1		T2	126		T3	480		T5	27
valid_sources[0x3e]	340010	1		T2	125		T3	213		T5	82
valid_sources[0x3f]	336934	1		T2	114		T3	201		T5	64
valid_sources[0x40]	340100	1		T2	84		T3	427		T5	49
valid_sources[0x41]	336976	1		T2	102		T5	153		T7	854
valid_sources[0x42]	342779	1		T2	123		T3	270		T5	140
valid_sources[0x43]	1280554	1		T2	72		T3	722		T5	32
valid_sources[0x44]	362049	1		T2	111		T3	105		T5	36
valid_sources[0x45]	353718	1		T2	83		T3	113		T5	42
valid_sources[0x46]	337505	1		T2	110		T3	110		T5	145
valid_sources[0x47]	794886	1		T2	84		T3	253		T5	107
valid_sources[0x48]	339039	1		T2	107		T3	958		T5	37
valid_sources[0x49]	348598	1		T2	91		T3	12065		T5	146
valid_sources[0x4a]	337755	1		T2	102		T3	235		T5	39
valid_sources[0x4b]	337977	1		T2	102		T5	123		T7	833
valid_sources[0x4c]	738411	1		T2	94		T3	101		T5	119
valid_sources[0x4d]	337240	1		T2	99		T3	118		T5	133
valid_sources[0x4e]	335887	1		T2	95		T3	216		T5	51
valid_sources[0x4f]	340934	1		T2	103		T3	295		T5	38
valid_sources[0x50]	510343	1		T2	108		T3	610		T5	92
valid_sources[0x51]	338992	1		T2	115		T3	344		T5	104
valid_sources[0x52]	338698	1		T2	115		T3	514		T5	46
valid_sources[0x53]	339646	1		T2	97		T3	47		T5	90
valid_sources[0x54]	336842	1		T2	88		T3	1		T5	41
valid_sources[0x55]	450416	1		T2	107		T3	101		T5	95
valid_sources[0x56]	337321	1		T2	102		T3	458		T5	58
valid_sources[0x57]	334868	1		T2	72		T3	17		T5	143
valid_sources[0x58]	341031	1		T2	97		T3	83		T5	70
valid_sources[0x59]	338805	1		T2	79		T3	224		T5	208
valid_sources[0x5a]	337411	1		T2	120		T3	699		T5	71
valid_sources[0x5b]	340471	1		T2	107		T3	83		T5	189
valid_sources[0x5c]	341685	1		T2	105		T3	291		T5	72
valid_sources[0x5d]	337657	1		T2	116		T3	71		T5	73
valid_sources[0x5e]	344690	1		T2	102		T3	552		T5	84
valid_sources[0x5f]	794785	1		T2	87		T3	154		T5	86
valid_sources[0x60]	336186	1		T2	93		T3	1		T5	38
valid_sources[0x61]	373221	1		T2	96		T3	1		T5	22
valid_sources[0x62]	351024	1		T2	115		T5	103		T7	845
valid_sources[0x63]	340014	1		T2	73		T3	4		T5	41
valid_sources[0x64]	687845	1		T2	92		T3	1		T5	58
valid_sources[0x65]	338633	1		T2	97		T3	18		T5	63
valid_sources[0x66]	338372	1		T2	98		T3	1		T5	117
valid_sources[0x67]	341066	1		T2	96		T3	823		T5	109
valid_sources[0x68]	336784	1		T2	82		T5	76		T7	849
valid_sources[0x69]	335725	1		T2	100		T3	278		T5	75
valid_sources[0x6a]	3648217	1		T2	75		T3	100		T5	76
valid_sources[0x6b]	961273	1		T2	89		T3	418		T5	18
valid_sources[0x6c]	338190	1		T2	84		T3	91		T5	141
valid_sources[0x6d]	338286	1		T2	95		T3	100		T5	84
valid_sources[0x6e]	809833	1		T2	112		T3	233		T5	64
valid_sources[0x6f]	342903	1		T2	95		T5	70		T7	893
valid_sources[0x70]	340875	1		T2	129		T3	10		T5	76
valid_sources[0x71]	373295	1		T2	109		T3	2		T5	130
valid_sources[0x72]	342753	1		T2	86		T3	244		T5	77
valid_sources[0x73]	339432	1		T2	99		T3	97		T5	124
valid_sources[0x74]	339696	1		T2	89		T5	54		T7	877
valid_sources[0x75]	339896	1		T2	98		T3	75		T5	33
valid_sources[0x76]	338177	1		T2	91		T3	46		T5	80
valid_sources[0x77]	691363	1		T2	103		T3	209		T5	91
valid_sources[0x78]	339600	1		T2	110		T3	166		T5	133
valid_sources[0x79]	341348	1		T2	112		T3	97		T5	47
valid_sources[0x7a]	399890	1		T2	107		T3	60		T5	41
valid_sources[0x7b]	337988	1		T2	104		T3	190		T5	73
valid_sources[0x7c]	750577	1		T2	103		T3	59		T5	81
valid_sources[0x7d]	339560	1		T2	92		T3	223		T5	158
valid_sources[0x7e]	341451	1		T2	79		T3	148		T5	152
valid_sources[0x7f]	391836	1		T2	104		T3	115		T5	54
valid_sources[0x80]	341484	1		T2	98		T3	471		T5	51

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

57672636

1

T1

1860

T2

6416

T3

18842

values[0x0]

all_enables

biggest_size

412081

1

T1

10

T2

8263

T3

17225

values[0x1]

all_enables

biggest_size

409961

1

T1

7

T2

8160

T3

17189