Module Definition
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Module : rv_timer_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_timer_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_timer_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_timer_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 2147483647 1429680 0 0
cfg0_rd_A 2147483647 6211 0 0
compare_lower0_0_rd_A 2147483647 6893 0 0
compare_upper0_0_rd_A 2147483647 5865 0 0
ctrl_rd_A 2147483647 5800 0 0
intr_enable0_rd_A 2147483647 7291 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1429680 0 0
T2 852379 27850 0 0
T3 452450 58191 0 0
T4 334038 0 0 0
T5 161560 0 0 0
T6 512005 0 0 0
T7 453026 0 0 0
T8 446401 0 0 0
T9 756307 220097 0 0
T10 283651 0 0 0
T30 0 29277 0 0
T31 0 219196 0 0
T32 0 160912 0 0
T33 0 119182 0 0
T34 0 75303 0 0
T35 0 77985 0 0
T36 0 106565 0 0
T37 173924 0 0 0

cfg0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6211 0 0
T11 4256 0 0 0
T16 377860 0 0 0
T17 168137 0 0 0
T18 404042 0 0 0
T19 133032 0 0 0
T20 268978 0 0 0
T25 0 157 0 0
T28 0 113 0 0
T30 115382 398 0 0
T32 0 1480 0 0
T34 0 689 0 0
T36 0 1150 0 0
T38 0 384 0 0
T39 0 34 0 0
T40 0 8 0 0
T41 0 18 0 0
T42 130722 0 0 0
T43 704006 0 0 0
T44 114309 0 0 0

compare_lower0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6893 0 0
T11 4256 0 0 0
T16 377860 0 0 0
T17 168137 0 0 0
T18 404042 0 0 0
T19 133032 0 0 0
T20 268978 0 0 0
T25 0 106 0 0
T28 0 102 0 0
T30 115382 381 0 0
T32 0 1987 0 0
T34 0 763 0 0
T36 0 1383 0 0
T38 0 378 0 0
T39 0 9 0 0
T40 0 4 0 0
T41 0 12 0 0
T42 130722 0 0 0
T43 704006 0 0 0
T44 114309 0 0 0

compare_upper0_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5865 0 0
T11 4256 0 0 0
T16 377860 0 0 0
T17 168137 0 0 0
T18 404042 0 0 0
T19 133032 0 0 0
T20 268978 0 0 0
T25 0 126 0 0
T28 0 130 0 0
T30 115382 282 0 0
T32 0 1458 0 0
T34 0 721 0 0
T36 0 1083 0 0
T38 0 362 0 0
T39 0 62 0 0
T40 0 9 0 0
T41 0 19 0 0
T42 130722 0 0 0
T43 704006 0 0 0
T44 114309 0 0 0

ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5800 0 0
T11 4256 0 0 0
T16 377860 0 0 0
T17 168137 0 0 0
T18 404042 0 0 0
T19 133032 0 0 0
T20 268978 0 0 0
T25 0 84 0 0
T28 0 126 0 0
T30 115382 256 0 0
T32 0 1649 0 0
T34 0 740 0 0
T36 0 1061 0 0
T38 0 241 0 0
T39 0 36 0 0
T40 0 7 0 0
T41 0 12 0 0
T42 130722 0 0 0
T43 704006 0 0 0
T44 114309 0 0 0

intr_enable0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 7291 0 0
T10 283651 5 0 0
T11 4256 0 0 0
T16 377860 0 0 0
T17 168137 0 0 0
T30 115382 417 0 0
T32 0 1855 0 0
T37 173924 0 0 0
T42 130722 0 0 0
T43 704006 0 0 0
T44 114309 0 0 0
T45 0 141 0 0
T46 0 40 0 0
T47 0 61 0 0
T48 0 25 0 0
T49 0 20 0 0
T50 0 37 0 0
T51 0 65 0 0
T52 153552 0 0 0

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