Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 576
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3793795949 Jun 28 06:18:22 PM PDT 24 Jun 28 06:18:29 PM PDT 24 13433011 ps
T509 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.779039657 Jun 28 06:18:45 PM PDT 24 Jun 28 06:18:48 PM PDT 24 252039740 ps
T510 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3697074530 Jun 28 06:18:35 PM PDT 24 Jun 28 06:18:37 PM PDT 24 17272586 ps
T511 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2927390728 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:55 PM PDT 24 11713602 ps
T512 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3162724349 Jun 28 06:18:43 PM PDT 24 Jun 28 06:18:45 PM PDT 24 41246225 ps
T513 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3989836850 Jun 28 06:18:54 PM PDT 24 Jun 28 06:19:04 PM PDT 24 21720056 ps
T102 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4064900142 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:54 PM PDT 24 247328880 ps
T514 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2218512431 Jun 28 06:18:21 PM PDT 24 Jun 28 06:18:28 PM PDT 24 18909970 ps
T515 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1793667044 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:57 PM PDT 24 60650645 ps
T516 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1304649795 Jun 28 06:18:33 PM PDT 24 Jun 28 06:18:36 PM PDT 24 18418751 ps
T517 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3715770316 Jun 28 06:18:23 PM PDT 24 Jun 28 06:18:31 PM PDT 24 24028342 ps
T518 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2502582512 Jun 28 06:18:23 PM PDT 24 Jun 28 06:18:30 PM PDT 24 67574715 ps
T519 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3164968487 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:54 PM PDT 24 32167407 ps
T520 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1578012636 Jun 28 06:18:46 PM PDT 24 Jun 28 06:18:51 PM PDT 24 38274358 ps
T521 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1909205714 Jun 28 06:18:31 PM PDT 24 Jun 28 06:18:35 PM PDT 24 36927215 ps
T522 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3661916424 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:57 PM PDT 24 14026734 ps
T523 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.97180803 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:55 PM PDT 24 231949117 ps
T524 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2131301353 Jun 28 06:18:21 PM PDT 24 Jun 28 06:18:28 PM PDT 24 34454700 ps
T525 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2898616745 Jun 28 06:18:50 PM PDT 24 Jun 28 06:18:59 PM PDT 24 32563201 ps
T526 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1997069347 Jun 28 06:18:50 PM PDT 24 Jun 28 06:18:58 PM PDT 24 54855850 ps
T527 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3042456735 Jun 28 06:18:44 PM PDT 24 Jun 28 06:18:48 PM PDT 24 129872511 ps
T528 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2663609708 Jun 28 06:18:55 PM PDT 24 Jun 28 06:19:04 PM PDT 24 42781805 ps
T529 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3929194709 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:52 PM PDT 24 13899278 ps
T87 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1741182356 Jun 28 06:18:22 PM PDT 24 Jun 28 06:18:30 PM PDT 24 13475764 ps
T530 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.865318634 Jun 28 06:18:43 PM PDT 24 Jun 28 06:18:45 PM PDT 24 32036998 ps
T531 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.558200936 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:00 PM PDT 24 80942136 ps
T532 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2819572300 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:52 PM PDT 24 65094589 ps
T88 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4036447568 Jun 28 06:18:15 PM PDT 24 Jun 28 06:18:24 PM PDT 24 15665676 ps
T533 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.940807398 Jun 28 06:18:43 PM PDT 24 Jun 28 06:18:45 PM PDT 24 19573781 ps
T534 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2624414425 Jun 28 06:18:28 PM PDT 24 Jun 28 06:18:33 PM PDT 24 44995271 ps
T535 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.300730329 Jun 28 06:18:52 PM PDT 24 Jun 28 06:19:03 PM PDT 24 209515181 ps
T536 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1184967272 Jun 28 06:18:26 PM PDT 24 Jun 28 06:18:33 PM PDT 24 132627666 ps
T537 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2396807264 Jun 28 06:18:44 PM PDT 24 Jun 28 06:18:46 PM PDT 24 258221137 ps
T538 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2989568762 Jun 28 06:18:13 PM PDT 24 Jun 28 06:18:21 PM PDT 24 45597375 ps
T539 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.542741395 Jun 28 06:18:51 PM PDT 24 Jun 28 06:19:01 PM PDT 24 14736367 ps
T540 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3465489162 Jun 28 06:18:36 PM PDT 24 Jun 28 06:18:38 PM PDT 24 52994339 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1490178400 Jun 28 06:18:17 PM PDT 24 Jun 28 06:18:25 PM PDT 24 42431263 ps
T541 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2804164805 Jun 28 06:18:35 PM PDT 24 Jun 28 06:18:36 PM PDT 24 88710078 ps
T542 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1321823916 Jun 28 06:18:51 PM PDT 24 Jun 28 06:18:59 PM PDT 24 38170902 ps
T543 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1151728254 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:53 PM PDT 24 43128539 ps
T544 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4221278943 Jun 28 06:18:44 PM PDT 24 Jun 28 06:18:46 PM PDT 24 12700194 ps
T545 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4243968703 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:56 PM PDT 24 48086674 ps
T90 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2358788558 Jun 28 06:18:25 PM PDT 24 Jun 28 06:18:32 PM PDT 24 24065332 ps
T546 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3805981989 Jun 28 06:18:46 PM PDT 24 Jun 28 06:18:50 PM PDT 24 46596016 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1384545958 Jun 28 06:18:21 PM PDT 24 Jun 28 06:18:28 PM PDT 24 16229591 ps
T548 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2944388255 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:57 PM PDT 24 43538804 ps
T549 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2118129145 Jun 28 06:18:25 PM PDT 24 Jun 28 06:18:32 PM PDT 24 20428238 ps
T550 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2046945213 Jun 28 06:18:22 PM PDT 24 Jun 28 06:18:30 PM PDT 24 112617249 ps
T551 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.583493478 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:55 PM PDT 24 15223341 ps
T552 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3950559968 Jun 28 06:18:49 PM PDT 24 Jun 28 06:19:02 PM PDT 24 23215983 ps
T553 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.554976673 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:55 PM PDT 24 40390850 ps
T554 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1746755388 Jun 28 06:18:40 PM PDT 24 Jun 28 06:18:42 PM PDT 24 18510839 ps
T555 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1303426242 Jun 28 06:18:23 PM PDT 24 Jun 28 06:18:32 PM PDT 24 236374885 ps
T556 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3123801530 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:55 PM PDT 24 38681689 ps
T557 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3018018989 Jun 28 06:18:53 PM PDT 24 Jun 28 06:19:03 PM PDT 24 43723983 ps
T558 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2357124801 Jun 28 06:18:19 PM PDT 24 Jun 28 06:18:27 PM PDT 24 82163800 ps
T559 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3853634412 Jun 28 06:18:58 PM PDT 24 Jun 28 06:19:07 PM PDT 24 264172251 ps
T560 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2574688810 Jun 28 06:18:40 PM PDT 24 Jun 28 06:18:42 PM PDT 24 32030559 ps
T561 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2180291068 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:57 PM PDT 24 308182479 ps
T562 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1032271532 Jun 28 06:18:48 PM PDT 24 Jun 28 06:18:54 PM PDT 24 17106224 ps
T563 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.943863579 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:51 PM PDT 24 41340674 ps
T564 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2651344344 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:56 PM PDT 24 17284105 ps
T565 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2324336176 Jun 28 06:18:50 PM PDT 24 Jun 28 06:18:59 PM PDT 24 184078366 ps
T566 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2043646304 Jun 28 06:18:22 PM PDT 24 Jun 28 06:18:30 PM PDT 24 17545102 ps
T91 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3794495871 Jun 28 06:18:26 PM PDT 24 Jun 28 06:18:32 PM PDT 24 26936969 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.312530683 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:54 PM PDT 24 82979861 ps
T568 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.286470295 Jun 28 06:18:21 PM PDT 24 Jun 28 06:18:29 PM PDT 24 52683634 ps
T569 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2724712499 Jun 28 06:18:23 PM PDT 24 Jun 28 06:18:30 PM PDT 24 22675287 ps
T570 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1182294312 Jun 28 06:18:20 PM PDT 24 Jun 28 06:18:28 PM PDT 24 70836978 ps
T571 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1943400663 Jun 28 06:18:15 PM PDT 24 Jun 28 06:18:24 PM PDT 24 22279114 ps
T572 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1136145883 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:52 PM PDT 24 16334114 ps
T573 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3176202335 Jun 28 06:18:49 PM PDT 24 Jun 28 06:18:56 PM PDT 24 41843662 ps
T574 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3554123666 Jun 28 06:18:53 PM PDT 24 Jun 28 06:19:03 PM PDT 24 12118313 ps
T105 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.899058514 Jun 28 06:18:47 PM PDT 24 Jun 28 06:18:54 PM PDT 24 156554142 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1388249252 Jun 28 06:18:20 PM PDT 24 Jun 28 06:18:28 PM PDT 24 191104377 ps
T576 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4150217710 Jun 28 06:18:37 PM PDT 24 Jun 28 06:18:39 PM PDT 24 12192051 ps

Test location /workspace/coverage/default/46.rv_timer_stress_all.3809915616
Short name T10
Test name
Test status
Simulation time 380758280153 ps
CPU time 340.42 seconds
Started Jun 28 07:20:43 PM PDT 24
Finished Jun 28 07:26:31 PM PDT 24
Peak memory 195736 kb
Host smart-6492f332-61dc-41e6-8ef4-5b902e3a6911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809915616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3809915616
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1266078322
Short name T15
Test name
Test status
Simulation time 76027552576 ps
CPU time 626.01 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:30:01 PM PDT 24
Peak memory 205988 kb
Host smart-67c84619-e932-466d-95f8-4c90349ca62c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266078322 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.1266078322
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2012704581
Short name T47
Test name
Test status
Simulation time 673388345124 ps
CPU time 2795.68 seconds
Started Jun 28 07:20:25 PM PDT 24
Finished Jun 28 08:07:16 PM PDT 24
Peak memory 191456 kb
Host smart-6132467a-f333-46f2-9e69-f907e9234ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012704581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2012704581
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1682264668
Short name T30
Test name
Test status
Simulation time 470213012 ps
CPU time 1.12 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 06:18:24 PM PDT 24
Peak memory 194720 kb
Host smart-5420a3b7-b2c9-4ee8-994c-337977b615d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682264668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1682264668
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2870514168
Short name T129
Test name
Test status
Simulation time 602313348769 ps
CPU time 1002.2 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:36:12 PM PDT 24
Peak memory 191356 kb
Host smart-8e8a792d-e0f1-4536-862d-90e7e3ee29b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870514168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2870514168
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1699443065
Short name T137
Test name
Test status
Simulation time 496392697081 ps
CPU time 3540.76 seconds
Started Jun 28 07:19:12 PM PDT 24
Finished Jun 28 08:18:38 PM PDT 24
Peak memory 191264 kb
Host smart-edf5361e-e18d-4957-92c4-728ccc2025f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699443065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1699443065
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.4040889903
Short name T29
Test name
Test status
Simulation time 487760177537 ps
CPU time 4335.52 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 08:31:51 PM PDT 24
Peak memory 195408 kb
Host smart-d1aef003-7d19-4481-bbfd-8b6c1dcbcc75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040889903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4040889903
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3292048025
Short name T67
Test name
Test status
Simulation time 362036245314 ps
CPU time 1121.57 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:38:17 PM PDT 24
Peak memory 195932 kb
Host smart-fc9cc0a7-b40b-4dae-a9d3-258d904fc022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292048025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3292048025
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2038677419
Short name T125
Test name
Test status
Simulation time 2707187805299 ps
CPU time 5147.74 seconds
Started Jun 28 07:19:40 PM PDT 24
Finished Jun 28 08:45:46 PM PDT 24
Peak memory 191364 kb
Host smart-d021679f-1bd9-43a0-aaf2-1f2f2b57ee8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038677419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2038677419
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1729517955
Short name T80
Test name
Test status
Simulation time 670120582 ps
CPU time 2.38 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 06:18:25 PM PDT 24
Peak memory 193472 kb
Host smart-da1021ac-347b-4c04-9705-0e77d3ae28b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729517955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1729517955
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2361902363
Short name T19
Test name
Test status
Simulation time 732244560 ps
CPU time 0.81 seconds
Started Jun 28 07:19:02 PM PDT 24
Finished Jun 28 07:19:26 PM PDT 24
Peak memory 213416 kb
Host smart-28ccba7e-bb3e-4d4b-8c37-ee692a0fd2aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361902363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2361902363
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3845998057
Short name T170
Test name
Test status
Simulation time 1255095811764 ps
CPU time 1067.78 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:37:17 PM PDT 24
Peak memory 191360 kb
Host smart-37a28a8a-25bc-4dec-80bf-778351aa9452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845998057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3845998057
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/87.rv_timer_random.2256753778
Short name T13
Test name
Test status
Simulation time 441043757388 ps
CPU time 312.38 seconds
Started Jun 28 07:21:29 PM PDT 24
Finished Jun 28 07:26:47 PM PDT 24
Peak memory 191360 kb
Host smart-6d66856d-b38a-45f2-b117-01890b3937bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256753778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2256753778
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.559934318
Short name T136
Test name
Test status
Simulation time 532202234132 ps
CPU time 1294.51 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:41:08 PM PDT 24
Peak memory 191224 kb
Host smart-107b97f3-ba7a-4566-bba8-e346d8b1009c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559934318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
559934318
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/106.rv_timer_random.3309733381
Short name T124
Test name
Test status
Simulation time 130271931612 ps
CPU time 717.74 seconds
Started Jun 28 07:21:46 PM PDT 24
Finished Jun 28 07:33:48 PM PDT 24
Peak memory 191336 kb
Host smart-9afa2623-7e0d-4375-8086-1ae9ad549903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309733381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3309733381
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3489700803
Short name T162
Test name
Test status
Simulation time 1695261370363 ps
CPU time 2916.41 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 08:08:06 PM PDT 24
Peak memory 196040 kb
Host smart-1f190959-850c-4da5-9552-6f7004613c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489700803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3489700803
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/76.rv_timer_random.1041911014
Short name T274
Test name
Test status
Simulation time 106481468078 ps
CPU time 251.59 seconds
Started Jun 28 07:21:30 PM PDT 24
Finished Jun 28 07:25:47 PM PDT 24
Peak memory 191296 kb
Host smart-e37e9bfa-042b-4b4f-89ac-2f448dbbadbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041911014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1041911014
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2914087344
Short name T247
Test name
Test status
Simulation time 347818233572 ps
CPU time 938.4 seconds
Started Jun 28 07:21:43 PM PDT 24
Finished Jun 28 07:37:26 PM PDT 24
Peak memory 191324 kb
Host smart-1e427a59-f693-4188-a766-dbb8474014ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914087344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2914087344
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3874044760
Short name T217
Test name
Test status
Simulation time 627496258793 ps
CPU time 680.46 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:33:20 PM PDT 24
Peak memory 191352 kb
Host smart-0a516d23-a150-4c52-a3a7-40cc80c2db06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874044760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3874044760
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3786586422
Short name T334
Test name
Test status
Simulation time 663048147777 ps
CPU time 1414.82 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:45:35 PM PDT 24
Peak memory 191372 kb
Host smart-813af653-a689-476d-ad54-8bbbe5e9cc1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786586422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3786586422
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1897939584
Short name T211
Test name
Test status
Simulation time 707472380414 ps
CPU time 1258.65 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:42:11 PM PDT 24
Peak memory 193720 kb
Host smart-874400cd-9973-42ec-9f65-d432358fb763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897939584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1897939584
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.2033878081
Short name T176
Test name
Test status
Simulation time 226904044963 ps
CPU time 306.33 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:27:06 PM PDT 24
Peak memory 191368 kb
Host smart-b79ec4aa-1064-4729-9662-7c8b75a0f341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033878081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2033878081
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1376598637
Short name T151
Test name
Test status
Simulation time 567372510890 ps
CPU time 317.79 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:27:39 PM PDT 24
Peak memory 191360 kb
Host smart-6c391959-4daa-4473-b8d0-eb90251cbc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376598637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1376598637
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4114179526
Short name T128
Test name
Test status
Simulation time 133170352347 ps
CPU time 572.33 seconds
Started Jun 28 07:22:56 PM PDT 24
Finished Jun 28 07:32:32 PM PDT 24
Peak memory 191336 kb
Host smart-e0d94b0a-a58f-4b30-9b25-6e9df021fd07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114179526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4114179526
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2838768463
Short name T259
Test name
Test status
Simulation time 189669063144 ps
CPU time 328.4 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:25:03 PM PDT 24
Peak memory 191324 kb
Host smart-de3b9986-c923-4321-b653-9c8212fbdeaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838768463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2838768463
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_random.925024954
Short name T152
Test name
Test status
Simulation time 712200074388 ps
CPU time 318.99 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:23:47 PM PDT 24
Peak memory 191344 kb
Host smart-8fdfbc2e-6217-43c0-b72e-53ea50d427f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925024954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.925024954
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3035185580
Short name T178
Test name
Test status
Simulation time 734793178417 ps
CPU time 544.15 seconds
Started Jun 28 07:19:12 PM PDT 24
Finished Jun 28 07:28:41 PM PDT 24
Peak memory 191352 kb
Host smart-5a4de8ce-b6a8-4f4b-817d-226f57d09a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035185580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3035185580
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1987907703
Short name T168
Test name
Test status
Simulation time 2612339214686 ps
CPU time 1937.51 seconds
Started Jun 28 07:19:25 PM PDT 24
Finished Jun 28 07:52:01 PM PDT 24
Peak memory 196156 kb
Host smart-e2af1c73-3924-4ff0-8e2c-45bd85e78bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987907703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1987907703
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2663736046
Short name T190
Test name
Test status
Simulation time 250478501603 ps
CPU time 3490.41 seconds
Started Jun 28 07:19:51 PM PDT 24
Finished Jun 28 08:18:20 PM PDT 24
Peak memory 196532 kb
Host smart-17a15327-c6d0-4afe-be4f-86be329cfc99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663736046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2663736046
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.541193448
Short name T153
Test name
Test status
Simulation time 179476355625 ps
CPU time 543.49 seconds
Started Jun 28 07:21:41 PM PDT 24
Finished Jun 28 07:30:48 PM PDT 24
Peak memory 191376 kb
Host smart-4c9540e3-73ea-4a69-ac4f-20cf350cf101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541193448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.541193448
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.2218335410
Short name T7
Test name
Test status
Simulation time 129472765609 ps
CPU time 271.46 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:24:06 PM PDT 24
Peak memory 194476 kb
Host smart-77bef3d4-5dfb-4e2b-bb39-a8d687e6dd59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218335410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2218335410
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.1941103814
Short name T126
Test name
Test status
Simulation time 591624931820 ps
CPU time 530.42 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:28:25 PM PDT 24
Peak memory 191364 kb
Host smart-0384cbf6-e7e2-4187-8b5e-4b6174bcf35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941103814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1941103814
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.51652350
Short name T224
Test name
Test status
Simulation time 456633434707 ps
CPU time 495.87 seconds
Started Jun 28 07:20:27 PM PDT 24
Finished Jun 28 07:28:57 PM PDT 24
Peak memory 191376 kb
Host smart-9fb52578-dcbe-426f-a1be-81f99743f7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51652350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.51652350
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1376887322
Short name T302
Test name
Test status
Simulation time 3978731882815 ps
CPU time 3807.96 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 08:24:07 PM PDT 24
Peak memory 196380 kb
Host smart-e69bf567-8a72-4f68-80e1-f02e3e6144be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376887322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1376887322
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/138.rv_timer_random.2210400889
Short name T193
Test name
Test status
Simulation time 1510390615603 ps
CPU time 487.11 seconds
Started Jun 28 07:21:56 PM PDT 24
Finished Jun 28 07:30:06 PM PDT 24
Peak memory 191360 kb
Host smart-6f4eae70-3895-4991-ab58-43c9279ddbdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210400889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2210400889
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1199985699
Short name T172
Test name
Test status
Simulation time 136955217294 ps
CPU time 426.27 seconds
Started Jun 28 07:21:58 PM PDT 24
Finished Jun 28 07:29:06 PM PDT 24
Peak memory 191340 kb
Host smart-c1643d4f-3417-48c4-8cf0-a5bba2b18cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199985699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1199985699
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.843440849
Short name T142
Test name
Test status
Simulation time 206583874443 ps
CPU time 276.59 seconds
Started Jun 28 07:21:56 PM PDT 24
Finished Jun 28 07:26:36 PM PDT 24
Peak memory 191308 kb
Host smart-7919a6a9-60c0-4eff-a784-9f4db5a88f89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843440849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.843440849
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.391939988
Short name T116
Test name
Test status
Simulation time 154551315843 ps
CPU time 451.29 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:30:29 PM PDT 24
Peak memory 191360 kb
Host smart-8842a256-6d78-4a91-8654-f6a4f4045aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391939988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.391939988
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2544708780
Short name T266
Test name
Test status
Simulation time 233307348854 ps
CPU time 411.73 seconds
Started Jun 28 07:19:47 PM PDT 24
Finished Jun 28 07:26:57 PM PDT 24
Peak memory 183136 kb
Host smart-afa4346c-3ff6-4de2-9c6e-24a732349515
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544708780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2544708780
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/95.rv_timer_random.152360311
Short name T322
Test name
Test status
Simulation time 42640120590 ps
CPU time 62.84 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:22:36 PM PDT 24
Peak memory 191208 kb
Host smart-a7738d04-9350-4ede-97c2-34a556151f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152360311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.152360311
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1679033392
Short name T263
Test name
Test status
Simulation time 248688069072 ps
CPU time 321.99 seconds
Started Jun 28 07:21:40 PM PDT 24
Finished Jun 28 07:27:05 PM PDT 24
Peak memory 194432 kb
Host smart-8bfba339-4f27-4e28-be6f-0ec1d3560c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679033392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1679033392
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2172516174
Short name T290
Test name
Test status
Simulation time 902691361541 ps
CPU time 511.94 seconds
Started Jun 28 07:19:21 PM PDT 24
Finished Jun 28 07:28:13 PM PDT 24
Peak memory 191364 kb
Host smart-2bef7a4b-8c2d-42c9-9514-62050d830ece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172516174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2172516174
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2761219444
Short name T229
Test name
Test status
Simulation time 921512422801 ps
CPU time 403.91 seconds
Started Jun 28 07:19:47 PM PDT 24
Finished Jun 28 07:26:49 PM PDT 24
Peak memory 183140 kb
Host smart-b79904ef-a0ac-4331-90e5-4ad15c502e62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761219444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2761219444
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1035221653
Short name T119
Test name
Test status
Simulation time 1151894210834 ps
CPU time 1497.82 seconds
Started Jun 28 07:20:43 PM PDT 24
Finished Jun 28 07:45:49 PM PDT 24
Peak memory 191340 kb
Host smart-fc6f9a7a-3b04-4e1c-a975-40cfbc8bf7e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035221653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1035221653
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.68190961
Short name T213
Test name
Test status
Simulation time 401236978938 ps
CPU time 349.58 seconds
Started Jun 28 07:21:26 PM PDT 24
Finished Jun 28 07:27:21 PM PDT 24
Peak memory 191304 kb
Host smart-e5a61f97-3ab3-42f1-a47d-a5744771106e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68190961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.68190961
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.572306925
Short name T239
Test name
Test status
Simulation time 634564986764 ps
CPU time 2401.18 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:59:31 PM PDT 24
Peak memory 195848 kb
Host smart-7c3b8d31-7e6e-4dfa-9cfe-0feddaddf153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572306925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.572306925
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/74.rv_timer_random.2790978045
Short name T173
Test name
Test status
Simulation time 560645203268 ps
CPU time 436.15 seconds
Started Jun 28 07:21:25 PM PDT 24
Finished Jun 28 07:28:46 PM PDT 24
Peak memory 191332 kb
Host smart-5911c893-aad5-448c-a1e9-56e435156c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790978045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2790978045
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.812456456
Short name T308
Test name
Test status
Simulation time 244579949550 ps
CPU time 304.03 seconds
Started Jun 28 07:21:41 PM PDT 24
Finished Jun 28 07:26:49 PM PDT 24
Peak memory 191356 kb
Host smart-0b65d371-d69b-43e6-8942-4ae0b512fb2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812456456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.812456456
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3118210656
Short name T305
Test name
Test status
Simulation time 496398549080 ps
CPU time 829.03 seconds
Started Jun 28 07:21:43 PM PDT 24
Finished Jun 28 07:35:37 PM PDT 24
Peak memory 193916 kb
Host smart-d5d46138-6ee0-484d-99db-83036553ef74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118210656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3118210656
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.600354001
Short name T57
Test name
Test status
Simulation time 344609075918 ps
CPU time 356.19 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:28:53 PM PDT 24
Peak memory 191352 kb
Host smart-5d9c9470-6089-4410-8259-ec2956b1451f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600354001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.600354001
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.116905800
Short name T144
Test name
Test status
Simulation time 425519165821 ps
CPU time 1935.83 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:55:14 PM PDT 24
Peak memory 191360 kb
Host smart-07edf085-ed34-43d3-af0e-548397e641cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116905800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.116905800
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3013371584
Short name T220
Test name
Test status
Simulation time 1374938155027 ps
CPU time 1511.69 seconds
Started Jun 28 07:19:31 PM PDT 24
Finished Jun 28 07:45:00 PM PDT 24
Peak memory 191360 kb
Host smart-a315c92b-c3ed-47d5-8e64-16c5f8637398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013371584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3013371584
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.11339760
Short name T219
Test name
Test status
Simulation time 44852690476 ps
CPU time 1020.41 seconds
Started Jun 28 07:20:08 PM PDT 24
Finished Jun 28 07:37:26 PM PDT 24
Peak memory 191340 kb
Host smart-3e8b15ed-6b6a-4b5a-8a24-db1211d9c467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11339760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.11339760
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random.1961473787
Short name T1
Test name
Test status
Simulation time 390659401321 ps
CPU time 1820.33 seconds
Started Jun 28 07:20:26 PM PDT 24
Finished Jun 28 07:51:00 PM PDT 24
Peak memory 191464 kb
Host smart-b20720fb-3697-495a-b3ad-cd16baf000d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961473787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1961473787
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3601209667
Short name T325
Test name
Test status
Simulation time 1814232544648 ps
CPU time 1018.61 seconds
Started Jun 28 07:20:45 PM PDT 24
Finished Jun 28 07:37:52 PM PDT 24
Peak memory 183156 kb
Host smart-f42cc9c0-0da8-4ef2-9798-8da7dd3c4dd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601209667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3601209667
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3676491758
Short name T181
Test name
Test status
Simulation time 2143129031203 ps
CPU time 1212.04 seconds
Started Jun 28 07:20:45 PM PDT 24
Finished Jun 28 07:41:05 PM PDT 24
Peak memory 196008 kb
Host smart-49ccaffb-bc5f-425a-a5a8-30db8c9e8fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676491758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3676491758
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3697995590
Short name T92
Test name
Test status
Simulation time 61759581 ps
CPU time 0.61 seconds
Started Jun 28 06:18:18 PM PDT 24
Finished Jun 28 06:18:26 PM PDT 24
Peak memory 191556 kb
Host smart-82eabda1-c2d6-47fd-a06f-b710a8575d7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697995590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3697995590
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.417386456
Short name T202
Test name
Test status
Simulation time 4013826834340 ps
CPU time 557.74 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:28:52 PM PDT 24
Peak memory 196132 kb
Host smart-e24275d9-5847-4782-bec3-ed5810414b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417386456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
417386456
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/109.rv_timer_random.1950456046
Short name T252
Test name
Test status
Simulation time 246738427346 ps
CPU time 141.33 seconds
Started Jun 28 07:21:40 PM PDT 24
Finished Jun 28 07:24:04 PM PDT 24
Peak memory 191352 kb
Host smart-53770988-faa3-438a-b7e5-225bc77712f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950456046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1950456046
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.626808792
Short name T242
Test name
Test status
Simulation time 268368645399 ps
CPU time 248.87 seconds
Started Jun 28 07:21:40 PM PDT 24
Finished Jun 28 07:25:53 PM PDT 24
Peak memory 191364 kb
Host smart-ef611aa6-4e1b-4df6-9ec0-a57b5822d685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626808792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.626808792
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.1931670956
Short name T110
Test name
Test status
Simulation time 584467834705 ps
CPU time 621.64 seconds
Started Jun 28 07:22:02 PM PDT 24
Finished Jun 28 07:32:26 PM PDT 24
Peak memory 191356 kb
Host smart-7b0fbb8c-d8ec-4f4a-9914-fef6bd7bf258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931670956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1931670956
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1144415780
Short name T140
Test name
Test status
Simulation time 160434430119 ps
CPU time 438.1 seconds
Started Jun 28 07:22:18 PM PDT 24
Finished Jun 28 07:29:37 PM PDT 24
Peak memory 191364 kb
Host smart-84b4f5a7-05e1-4c06-99fd-5a7cfd7e5e32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144415780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1144415780
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1499149562
Short name T134
Test name
Test status
Simulation time 463295400688 ps
CPU time 205.69 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:26:24 PM PDT 24
Peak memory 195040 kb
Host smart-ed0d31b9-199b-421b-8c83-03ae58c3b0f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499149562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1499149562
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.864804510
Short name T27
Test name
Test status
Simulation time 316897489651 ps
CPU time 402.35 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:29:40 PM PDT 24
Peak memory 191364 kb
Host smart-395ac10c-95a7-4cad-9474-98e0c1248b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864804510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.864804510
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3651444383
Short name T108
Test name
Test status
Simulation time 43142337119 ps
CPU time 63.92 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:20:34 PM PDT 24
Peak memory 183156 kb
Host smart-9d3a0ed3-7734-496a-af01-428e6e0c223d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651444383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3651444383
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.4161241566
Short name T70
Test name
Test status
Simulation time 1664387509391 ps
CPU time 1331.07 seconds
Started Jun 28 07:19:12 PM PDT 24
Finished Jun 28 07:41:48 PM PDT 24
Peak memory 191352 kb
Host smart-7b0047c2-509a-4146-803e-4692846e8a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161241566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.4161241566
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random.581233216
Short name T272
Test name
Test status
Simulation time 474892079036 ps
CPU time 363.59 seconds
Started Jun 28 07:19:21 PM PDT 24
Finished Jun 28 07:25:44 PM PDT 24
Peak memory 191360 kb
Host smart-c4220d2a-45f9-48ce-87bf-539511e10fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581233216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.581233216
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.2138546920
Short name T204
Test name
Test status
Simulation time 73946832453 ps
CPU time 110.76 seconds
Started Jun 28 07:19:20 PM PDT 24
Finished Jun 28 07:21:32 PM PDT 24
Peak memory 191332 kb
Host smart-03052754-6da2-4dd9-a598-4dd42e3413b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138546920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2138546920
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2673637677
Short name T281
Test name
Test status
Simulation time 106760685919 ps
CPU time 180.22 seconds
Started Jun 28 07:19:23 PM PDT 24
Finished Jun 28 07:22:42 PM PDT 24
Peak memory 183148 kb
Host smart-eff844c7-0bed-43dc-9ac9-5db487da54be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673637677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2673637677
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.322654093
Short name T68
Test name
Test status
Simulation time 1647825496245 ps
CPU time 796.11 seconds
Started Jun 28 07:19:35 PM PDT 24
Finished Jun 28 07:33:07 PM PDT 24
Peak memory 195076 kb
Host smart-8ed66ece-b87f-4dd9-8b5d-fdca52ec54f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322654093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
322654093
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.3886646302
Short name T112
Test name
Test status
Simulation time 165548716122 ps
CPU time 545.57 seconds
Started Jun 28 07:21:08 PM PDT 24
Finished Jun 28 07:30:18 PM PDT 24
Peak memory 191364 kb
Host smart-e0776f0b-6234-4e18-8c1d-470b07955cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886646302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3886646302
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3965818522
Short name T115
Test name
Test status
Simulation time 384774538175 ps
CPU time 488.91 seconds
Started Jun 28 07:21:25 PM PDT 24
Finished Jun 28 07:29:40 PM PDT 24
Peak memory 191344 kb
Host smart-9d9f21d9-5edb-4d7f-9c9f-ec7e1aba2bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965818522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3965818522
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2874864683
Short name T8
Test name
Test status
Simulation time 684130806525 ps
CPU time 733.81 seconds
Started Jun 28 07:21:31 PM PDT 24
Finished Jun 28 07:33:49 PM PDT 24
Peak memory 191296 kb
Host smart-7f47e69f-4cda-4345-9bf9-8aa6c9ff07fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874864683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2874864683
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.46116024
Short name T161
Test name
Test status
Simulation time 54898337894 ps
CPU time 104.6 seconds
Started Jun 28 07:21:29 PM PDT 24
Finished Jun 28 07:23:19 PM PDT 24
Peak memory 191364 kb
Host smart-aa3384ed-0090-4869-970d-6ebd21f38723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46116024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.46116024
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1693250315
Short name T234
Test name
Test status
Simulation time 156612045542 ps
CPU time 1539 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:47:12 PM PDT 24
Peak memory 191360 kb
Host smart-c97e745d-7710-4fad-9a3c-1de22c6460c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693250315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1693250315
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.65814867
Short name T101
Test name
Test status
Simulation time 1503003653 ps
CPU time 1.1 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:27 PM PDT 24
Peak memory 194768 kb
Host smart-98d83421-aaae-4c68-878c-2f5cf754443a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65814867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_int
g_err.65814867
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.899058514
Short name T105
Test name
Test status
Simulation time 156554142 ps
CPU time 1.04 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 182936 kb
Host smart-7c0383a3-b8b7-415c-a5c2-f2ab90563b95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899058514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.899058514
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1245016450
Short name T187
Test name
Test status
Simulation time 8765967393 ps
CPU time 3.52 seconds
Started Jun 28 07:18:15 PM PDT 24
Finished Jun 28 07:18:29 PM PDT 24
Peak memory 183176 kb
Host smart-20e307d2-a000-48d3-9e8b-89b24f731ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245016450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1245016450
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.4288625086
Short name T35
Test name
Test status
Simulation time 61548698676 ps
CPU time 540.5 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:28:32 PM PDT 24
Peak memory 209524 kb
Host smart-ca5da7e4-8015-4360-a116-8765ad2f3337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288625086 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.4288625086
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_random.2232962574
Short name T295
Test name
Test status
Simulation time 1553541596034 ps
CPU time 421.83 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:26:32 PM PDT 24
Peak memory 191356 kb
Host smart-edbfc9e7-2066-4a25-81a2-ef70418868e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232962574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2232962574
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2135529788
Short name T74
Test name
Test status
Simulation time 324752156669 ps
CPU time 169.87 seconds
Started Jun 28 07:21:42 PM PDT 24
Finished Jun 28 07:24:36 PM PDT 24
Peak memory 191324 kb
Host smart-9443281b-0731-41e3-92d1-9a35c7cbe680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135529788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2135529788
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.847308040
Short name T169
Test name
Test status
Simulation time 374455164349 ps
CPU time 275.44 seconds
Started Jun 28 07:21:39 PM PDT 24
Finished Jun 28 07:26:17 PM PDT 24
Peak memory 191364 kb
Host smart-b1bcbc85-1b52-4072-a01c-16cc55d80426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847308040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.847308040
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.2892991829
Short name T312
Test name
Test status
Simulation time 194637783506 ps
CPU time 228.75 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:23:16 PM PDT 24
Peak memory 191344 kb
Host smart-3db3c5b0-f526-4521-8016-40209b397656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892991829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2892991829
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.369775321
Short name T269
Test name
Test status
Simulation time 122087374402 ps
CPU time 862.04 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:33:55 PM PDT 24
Peak memory 194604 kb
Host smart-ea1dbea2-2f66-44e3-aebf-89b47aca3187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369775321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.369775321
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/119.rv_timer_random.1084754534
Short name T238
Test name
Test status
Simulation time 80953691511 ps
CPU time 143.78 seconds
Started Jun 28 07:21:43 PM PDT 24
Finished Jun 28 07:24:12 PM PDT 24
Peak memory 191364 kb
Host smart-fe53fb66-87fe-4cbb-8726-f8b755802d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084754534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1084754534
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.580445304
Short name T316
Test name
Test status
Simulation time 42952474307 ps
CPU time 35.78 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:20:09 PM PDT 24
Peak memory 183184 kb
Host smart-491e7fc4-b58c-4527-8821-dc57da231ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580445304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.580445304
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/127.rv_timer_random.3022859389
Short name T253
Test name
Test status
Simulation time 184079890185 ps
CPU time 96.56 seconds
Started Jun 28 07:22:00 PM PDT 24
Finished Jun 28 07:23:39 PM PDT 24
Peak memory 183148 kb
Host smart-8c249757-561a-449b-ac5c-76055ab9e651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022859389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3022859389
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.1364177868
Short name T156
Test name
Test status
Simulation time 78787876787 ps
CPU time 52.87 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:20:28 PM PDT 24
Peak memory 191232 kb
Host smart-ba91efbf-9744-4875-aaf7-80cba3d70b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364177868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1364177868
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3351690491
Short name T109
Test name
Test status
Simulation time 119677463564 ps
CPU time 184.42 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:25:04 PM PDT 24
Peak memory 191396 kb
Host smart-e6c2d0c2-b84a-4ada-832c-4fbc92c97550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351690491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3351690491
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1897095624
Short name T183
Test name
Test status
Simulation time 596762235947 ps
CPU time 248.55 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:26:08 PM PDT 24
Peak memory 193944 kb
Host smart-a47ec950-ae87-4a16-8fe5-509843802972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897095624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1897095624
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.781116289
Short name T174
Test name
Test status
Simulation time 50474916265 ps
CPU time 82.17 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:23:44 PM PDT 24
Peak memory 194896 kb
Host smart-41722ff8-f141-4cf6-bcb5-cfaae742f35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781116289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.781116289
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3167510256
Short name T255
Test name
Test status
Simulation time 168703796333 ps
CPU time 132.48 seconds
Started Jun 28 07:22:20 PM PDT 24
Finished Jun 28 07:24:37 PM PDT 24
Peak memory 183120 kb
Host smart-63777797-5a7d-4bee-81d5-694b673cac1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167510256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3167510256
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.611079021
Short name T333
Test name
Test status
Simulation time 118672871727 ps
CPU time 194.08 seconds
Started Jun 28 07:19:13 PM PDT 24
Finished Jun 28 07:22:51 PM PDT 24
Peak memory 183156 kb
Host smart-361ff6ab-85e3-45f5-962f-88d2e04698ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611079021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.611079021
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/173.rv_timer_random.463723550
Short name T314
Test name
Test status
Simulation time 45697735696 ps
CPU time 210.04 seconds
Started Jun 28 07:22:52 PM PDT 24
Finished Jun 28 07:26:23 PM PDT 24
Peak memory 192388 kb
Host smart-2c3b4399-37eb-4832-a6fc-474e5c0422a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463723550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.463723550
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2430636794
Short name T248
Test name
Test status
Simulation time 488040636946 ps
CPU time 427.29 seconds
Started Jun 28 07:22:53 PM PDT 24
Finished Jun 28 07:30:04 PM PDT 24
Peak memory 191364 kb
Host smart-ec3a6f11-80fd-47cf-8b50-93bacca15f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430636794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2430636794
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.3609103506
Short name T56
Test name
Test status
Simulation time 67410959786 ps
CPU time 383.76 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:25:53 PM PDT 24
Peak memory 191344 kb
Host smart-d0d437c7-b2dc-481e-8e42-0d09ebe08fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609103506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3609103506
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.928716129
Short name T298
Test name
Test status
Simulation time 521393111863 ps
CPU time 412.96 seconds
Started Jun 28 07:22:53 PM PDT 24
Finished Jun 28 07:29:49 PM PDT 24
Peak memory 191364 kb
Host smart-b26460bf-3dac-40f4-96e3-228f6dc62022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928716129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.928716129
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.865930374
Short name T250
Test name
Test status
Simulation time 274880326474 ps
CPU time 1630.47 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:50:45 PM PDT 24
Peak memory 191360 kb
Host smart-faa8e9ac-40a2-4419-863a-5eb8558230fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865930374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.865930374
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.906446206
Short name T303
Test name
Test status
Simulation time 46605409613 ps
CPU time 88.54 seconds
Started Jun 28 07:23:34 PM PDT 24
Finished Jun 28 07:25:09 PM PDT 24
Peak memory 191364 kb
Host smart-779ebf20-cf05-4288-83f1-72ed2329fb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906446206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.906446206
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3042128205
Short name T141
Test name
Test status
Simulation time 560941921396 ps
CPU time 1894.62 seconds
Started Jun 28 07:23:32 PM PDT 24
Finished Jun 28 07:55:13 PM PDT 24
Peak memory 191356 kb
Host smart-27382122-e48d-490d-a5bb-22d9a482e88b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042128205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3042128205
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.524614279
Short name T192
Test name
Test status
Simulation time 411095788625 ps
CPU time 468.79 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:31:22 PM PDT 24
Peak memory 191360 kb
Host smart-a1c2e538-c93a-40a6-a00e-71e869ef1b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524614279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.524614279
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1525433914
Short name T226
Test name
Test status
Simulation time 366681993220 ps
CPU time 562.03 seconds
Started Jun 28 07:19:11 PM PDT 24
Finished Jun 28 07:28:58 PM PDT 24
Peak memory 183120 kb
Host smart-fa5d5730-7b19-41f4-8c3b-7e1b7832f6e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525433914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1525433914
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_random.3264331419
Short name T317
Test name
Test status
Simulation time 56819892270 ps
CPU time 281.68 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:24:16 PM PDT 24
Peak memory 191280 kb
Host smart-34e08b0e-2728-4853-bcf4-641ca3d4ac55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264331419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3264331419
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.588118296
Short name T3
Test name
Test status
Simulation time 51010362518 ps
CPU time 76.39 seconds
Started Jun 28 07:19:29 PM PDT 24
Finished Jun 28 07:21:04 PM PDT 24
Peak memory 183136 kb
Host smart-e757742c-beba-4c12-bf18-cf33f42350ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588118296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.588118296
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3346887217
Short name T46
Test name
Test status
Simulation time 731579712348 ps
CPU time 536.35 seconds
Started Jun 28 07:19:20 PM PDT 24
Finished Jun 28 07:28:37 PM PDT 24
Peak memory 183168 kb
Host smart-05a74f01-4850-4e02-9656-33f3431ff20d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346887217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3346887217
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1791828053
Short name T118
Test name
Test status
Simulation time 480661720762 ps
CPU time 865.37 seconds
Started Jun 28 07:19:23 PM PDT 24
Finished Jun 28 07:34:08 PM PDT 24
Peak memory 183136 kb
Host smart-f1ed47f6-8ad3-42cb-b0e1-e796d078d394
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791828053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1791828053
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3154523618
Short name T235
Test name
Test status
Simulation time 67474231616 ps
CPU time 77.69 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:20:47 PM PDT 24
Peak memory 183172 kb
Host smart-36197fa2-5e98-4b5b-a44c-069a711846e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154523618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3154523618
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_random.2071209486
Short name T123
Test name
Test status
Simulation time 237608360226 ps
CPU time 95.73 seconds
Started Jun 28 07:20:09 PM PDT 24
Finished Jun 28 07:22:02 PM PDT 24
Peak memory 191360 kb
Host smart-d305a1a7-18ad-463e-b546-10e63ee235f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071209486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2071209486
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1154446474
Short name T283
Test name
Test status
Simulation time 1526397668307 ps
CPU time 821.56 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:34:54 PM PDT 24
Peak memory 195920 kb
Host smart-f063d2d6-d724-4f27-a23c-c7a3d6043be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154446474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1154446474
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.154820536
Short name T338
Test name
Test status
Simulation time 43808840334 ps
CPU time 80.39 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:22:34 PM PDT 24
Peak memory 183168 kb
Host smart-74347bc6-59c0-4fd7-b54b-a54e3bd87dca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154820536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.154820536
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3365500880
Short name T499
Test name
Test status
Simulation time 62231585 ps
CPU time 0.64 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:27 PM PDT 24
Peak memory 191708 kb
Host smart-cfa88224-e931-44fc-9c54-0e09212f542d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365500880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3365500880
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1407225613
Short name T504
Test name
Test status
Simulation time 100959413 ps
CPU time 0.58 seconds
Started Jun 28 06:18:16 PM PDT 24
Finished Jun 28 06:18:24 PM PDT 24
Peak memory 182492 kb
Host smart-792798cc-c242-4a74-95b0-a024a3f614ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407225613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1407225613
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4079057071
Short name T482
Test name
Test status
Simulation time 26399991 ps
CPU time 0.85 seconds
Started Jun 28 06:18:26 PM PDT 24
Finished Jun 28 06:18:32 PM PDT 24
Peak memory 194904 kb
Host smart-f670e0d5-75bb-40f6-b3cb-ac533ade30f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079057071 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.4079057071
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1723047572
Short name T51
Test name
Test status
Simulation time 54183923 ps
CPU time 0.62 seconds
Started Jun 28 06:18:25 PM PDT 24
Finished Jun 28 06:18:32 PM PDT 24
Peak memory 182324 kb
Host smart-40bc9c37-9b5f-46bd-8a85-fb8ad6e196f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723047572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1723047572
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.300505549
Short name T468
Test name
Test status
Simulation time 43266979 ps
CPU time 0.6 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:31 PM PDT 24
Peak memory 182244 kb
Host smart-b0dadd7d-bf68-4d91-8e88-2fb51488d4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300505549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.300505549
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2048694996
Short name T469
Test name
Test status
Simulation time 315670827 ps
CPU time 1.4 seconds
Started Jun 28 06:18:19 PM PDT 24
Finished Jun 28 06:18:27 PM PDT 24
Peak memory 197072 kb
Host smart-86cc190a-b73e-4325-8c68-50a38063189a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048694996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2048694996
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3794495871
Short name T91
Test name
Test status
Simulation time 26936969 ps
CPU time 0.72 seconds
Started Jun 28 06:18:26 PM PDT 24
Finished Jun 28 06:18:32 PM PDT 24
Peak memory 192172 kb
Host smart-ccf1e7f3-f823-46d2-9039-e9a77450ea93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794495871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3794495871
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1653213539
Short name T495
Test name
Test status
Simulation time 252251487 ps
CPU time 1.6 seconds
Started Jun 28 06:18:13 PM PDT 24
Finished Jun 28 06:18:23 PM PDT 24
Peak memory 193256 kb
Host smart-0dcc4d48-1cd7-4fff-a24a-555d08178721
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653213539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1653213539
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4036447568
Short name T88
Test name
Test status
Simulation time 15665676 ps
CPU time 0.56 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 06:18:24 PM PDT 24
Peak memory 182336 kb
Host smart-ca32828d-e769-4965-b173-d8a09eefdb6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036447568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4036447568
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1388249252
Short name T575
Test name
Test status
Simulation time 191104377 ps
CPU time 1.58 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:28 PM PDT 24
Peak memory 197292 kb
Host smart-f99c2d24-de08-4d96-86e0-56953bdad689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388249252 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1388249252
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.317100125
Short name T481
Test name
Test status
Simulation time 106449254 ps
CPU time 0.54 seconds
Started Jun 28 06:18:19 PM PDT 24
Finished Jun 28 06:18:26 PM PDT 24
Peak memory 182328 kb
Host smart-61f8e283-7808-4d8e-9085-1dbca7c21de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317100125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.317100125
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1943400663
Short name T571
Test name
Test status
Simulation time 22279114 ps
CPU time 0.58 seconds
Started Jun 28 06:18:15 PM PDT 24
Finished Jun 28 06:18:24 PM PDT 24
Peak memory 181664 kb
Host smart-d27ebd76-b918-448c-8b18-7c36e3267d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943400663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1943400663
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3638794012
Short name T500
Test name
Test status
Simulation time 50817273 ps
CPU time 0.75 seconds
Started Jun 28 06:18:14 PM PDT 24
Finished Jun 28 06:18:22 PM PDT 24
Peak memory 191248 kb
Host smart-0bc8f692-80f1-4b01-b1e4-6e70d4910944
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638794012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3638794012
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.462765337
Short name T52
Test name
Test status
Simulation time 303746388 ps
CPU time 1.72 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:29 PM PDT 24
Peak memory 197112 kb
Host smart-026ab0ea-fb51-4e8d-9801-e75f2830c875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462765337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.462765337
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2357124801
Short name T558
Test name
Test status
Simulation time 82163800 ps
CPU time 1.13 seconds
Started Jun 28 06:18:19 PM PDT 24
Finished Jun 28 06:18:27 PM PDT 24
Peak memory 195020 kb
Host smart-3c39fcf4-d3f5-4db7-8ff5-4e4d37f9b851
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357124801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2357124801
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3465489162
Short name T540
Test name
Test status
Simulation time 52994339 ps
CPU time 0.87 seconds
Started Jun 28 06:18:36 PM PDT 24
Finished Jun 28 06:18:38 PM PDT 24
Peak memory 195436 kb
Host smart-bb7c6667-0394-4929-8b2e-71b3be5dc15b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465489162 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3465489162
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1384545958
Short name T547
Test name
Test status
Simulation time 16229591 ps
CPU time 0.53 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:28 PM PDT 24
Peak memory 182032 kb
Host smart-c5fe0140-09e2-4fa3-8c7b-44e0a6ad130c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384545958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1384545958
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1304649795
Short name T516
Test name
Test status
Simulation time 18418751 ps
CPU time 0.58 seconds
Started Jun 28 06:18:33 PM PDT 24
Finished Jun 28 06:18:36 PM PDT 24
Peak memory 182200 kb
Host smart-b00cb32a-447b-4ff2-8fa7-4571a86b4d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304649795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1304649795
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1746755388
Short name T554
Test name
Test status
Simulation time 18510839 ps
CPU time 0.82 seconds
Started Jun 28 06:18:40 PM PDT 24
Finished Jun 28 06:18:42 PM PDT 24
Peak memory 191276 kb
Host smart-57861da6-c7a6-4600-8793-a5f4be1031fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746755388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1746755388
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.417509157
Short name T455
Test name
Test status
Simulation time 317737831 ps
CPU time 1.68 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:29 PM PDT 24
Peak memory 197076 kb
Host smart-b5270bfa-ac78-458e-a401-7eb9f5d6ee20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417509157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.417509157
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3176202335
Short name T573
Test name
Test status
Simulation time 41843662 ps
CPU time 0.91 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:56 PM PDT 24
Peak memory 196956 kb
Host smart-b77486d1-cf54-4ceb-ab66-e195272079ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176202335 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3176202335
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1997069347
Short name T526
Test name
Test status
Simulation time 54855850 ps
CPU time 0.59 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:58 PM PDT 24
Peak memory 182332 kb
Host smart-3feced1e-c941-4b12-a193-cd148edb8def
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997069347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1997069347
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1136145883
Short name T572
Test name
Test status
Simulation time 16334114 ps
CPU time 0.56 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:52 PM PDT 24
Peak memory 182200 kb
Host smart-2791cc6d-3fa5-411a-a982-7c8b82b40e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136145883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1136145883
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1608411651
Short name T93
Test name
Test status
Simulation time 199253182 ps
CPU time 0.81 seconds
Started Jun 28 06:18:44 PM PDT 24
Finished Jun 28 06:18:47 PM PDT 24
Peak memory 193024 kb
Host smart-6aa08082-41fe-42e2-8479-a182022be522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608411651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1608411651
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3732184147
Short name T50
Test name
Test status
Simulation time 142833828 ps
CPU time 2.42 seconds
Started Jun 28 06:18:25 PM PDT 24
Finished Jun 28 06:18:34 PM PDT 24
Peak memory 197120 kb
Host smart-0f43c7e1-0318-4bd1-91f2-ed69fee60061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732184147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3732184147
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1151728254
Short name T543
Test name
Test status
Simulation time 43128539 ps
CPU time 1 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:53 PM PDT 24
Peak memory 196980 kb
Host smart-0cfd4f9b-69bf-43f0-9a18-d3a3532edf0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151728254 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1151728254
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3101278464
Short name T66
Test name
Test status
Simulation time 15140510 ps
CPU time 0.59 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 182260 kb
Host smart-e60aa8a9-d74c-4ab5-93b1-8e55252ff76e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101278464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3101278464
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.50453161
Short name T478
Test name
Test status
Simulation time 28266626 ps
CPU time 0.57 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:49 PM PDT 24
Peak memory 182196 kb
Host smart-5fba46ce-d3a0-4600-94f4-85943c3e1a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50453161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.50453161
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.472238561
Short name T507
Test name
Test status
Simulation time 21146777 ps
CPU time 0.77 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 191244 kb
Host smart-abe48e15-929a-4365-a9e3-8c52bef55ca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472238561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.472238561
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2324336176
Short name T565
Test name
Test status
Simulation time 184078366 ps
CPU time 2 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 197064 kb
Host smart-50eb6a18-8dbf-4027-927c-d7a5cbba48f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324336176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2324336176
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2203664643
Short name T99
Test name
Test status
Simulation time 64867247 ps
CPU time 0.86 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:50 PM PDT 24
Peak memory 193356 kb
Host smart-4246607a-76fe-4918-9407-1bbad5652f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203664643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2203664643
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2485364922
Short name T55
Test name
Test status
Simulation time 93612118 ps
CPU time 0.62 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:58 PM PDT 24
Peak memory 192648 kb
Host smart-c9bedfb5-cb23-4908-a616-4fd2ab194401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485364922 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2485364922
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3162724349
Short name T512
Test name
Test status
Simulation time 41246225 ps
CPU time 0.56 seconds
Started Jun 28 06:18:43 PM PDT 24
Finished Jun 28 06:18:45 PM PDT 24
Peak memory 182248 kb
Host smart-2a29c8d4-eb71-49db-94a3-ddf24075d9bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162724349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3162724349
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3989836850
Short name T513
Test name
Test status
Simulation time 21720056 ps
CPU time 0.56 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:04 PM PDT 24
Peak memory 182252 kb
Host smart-efc02ece-3ded-4a09-915c-6b36eb725eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989836850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3989836850
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3164968487
Short name T519
Test name
Test status
Simulation time 32167407 ps
CPU time 0.73 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 192772 kb
Host smart-1aa9e742-5bbe-48cd-bd23-42ef9346497c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164968487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3164968487
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2819572300
Short name T532
Test name
Test status
Simulation time 65094589 ps
CPU time 1.27 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:52 PM PDT 24
Peak memory 197052 kb
Host smart-7b67f323-464c-40c0-ba19-e7a109a33c46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819572300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2819572300
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1270371904
Short name T31
Test name
Test status
Simulation time 642896425 ps
CPU time 1.35 seconds
Started Jun 28 06:18:45 PM PDT 24
Finished Jun 28 06:18:48 PM PDT 24
Peak memory 195056 kb
Host smart-b7c87cba-69b2-4c2a-98c4-1061bf50c598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270371904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1270371904
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2743339067
Short name T485
Test name
Test status
Simulation time 56051549 ps
CPU time 0.61 seconds
Started Jun 28 06:18:53 PM PDT 24
Finished Jun 28 06:19:02 PM PDT 24
Peak memory 193016 kb
Host smart-76c9e0c3-bd10-40f5-8cd3-d85c12d1c14f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743339067 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2743339067
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1009073692
Short name T506
Test name
Test status
Simulation time 25533860 ps
CPU time 0.52 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 182232 kb
Host smart-049612e1-428b-49ae-82a9-f1fc1acbc76b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009073692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1009073692
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2428649890
Short name T492
Test name
Test status
Simulation time 47119976 ps
CPU time 0.56 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 182176 kb
Host smart-241342af-2df5-4572-a135-e59fe20174a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428649890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2428649890
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3810639031
Short name T79
Test name
Test status
Simulation time 70276874 ps
CPU time 0.65 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 191712 kb
Host smart-0fd80f62-a0a1-4c69-9660-71dd5d507e11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810639031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3810639031
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2396807264
Short name T537
Test name
Test status
Simulation time 258221137 ps
CPU time 1.33 seconds
Started Jun 28 06:18:44 PM PDT 24
Finished Jun 28 06:18:46 PM PDT 24
Peak memory 196880 kb
Host smart-c524f61e-3eb4-4aa4-bf53-e6f8f4f71318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396807264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2396807264
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3853634412
Short name T559
Test name
Test status
Simulation time 264172251 ps
CPU time 1.14 seconds
Started Jun 28 06:18:58 PM PDT 24
Finished Jun 28 06:19:07 PM PDT 24
Peak memory 194840 kb
Host smart-895156e5-806b-4425-afad-ae01f3285496
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853634412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3853634412
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.865318634
Short name T530
Test name
Test status
Simulation time 32036998 ps
CPU time 0.89 seconds
Started Jun 28 06:18:43 PM PDT 24
Finished Jun 28 06:18:45 PM PDT 24
Peak memory 196692 kb
Host smart-b09666b2-1cc6-4754-8c5d-a69cd6608952
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865318634 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.865318634
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3228739206
Short name T494
Test name
Test status
Simulation time 42847356 ps
CPU time 0.56 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:01 PM PDT 24
Peak memory 182180 kb
Host smart-dc651d8b-9320-4c8d-9a80-97faeb87d568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228739206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3228739206
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3018018989
Short name T557
Test name
Test status
Simulation time 43723983 ps
CPU time 0.57 seconds
Started Jun 28 06:18:53 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 181848 kb
Host smart-fb394b15-fe1a-4d70-a66d-e1588e1f619b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018018989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3018018989
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1793667044
Short name T515
Test name
Test status
Simulation time 60650645 ps
CPU time 0.71 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 191800 kb
Host smart-7f4321c2-7377-422c-9ffa-6dd36e693e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793667044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1793667044
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.779039657
Short name T509
Test name
Test status
Simulation time 252039740 ps
CPU time 1.13 seconds
Started Jun 28 06:18:45 PM PDT 24
Finished Jun 28 06:18:48 PM PDT 24
Peak memory 197116 kb
Host smart-c0acf3fa-353a-4f74-98c0-7bfc62a30f50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779039657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.779039657
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4064900142
Short name T102
Test name
Test status
Simulation time 247328880 ps
CPU time 1.38 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 194960 kb
Host smart-39321bbe-aeff-4ad2-b583-5ea458f537ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064900142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4064900142
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3077882384
Short name T488
Test name
Test status
Simulation time 171145498 ps
CPU time 0.84 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:49 PM PDT 24
Peak memory 196404 kb
Host smart-701b8d6c-6244-4a20-9057-24f353679d4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077882384 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3077882384
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3123801530
Short name T556
Test name
Test status
Simulation time 38681689 ps
CPU time 0.53 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 182116 kb
Host smart-56fc750a-2c6b-4512-8688-994928f54120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123801530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3123801530
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2651344344
Short name T564
Test name
Test status
Simulation time 17284105 ps
CPU time 0.62 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:56 PM PDT 24
Peak memory 182172 kb
Host smart-563bed72-ef47-4659-b0f3-e21532806bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651344344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2651344344
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3950559968
Short name T552
Test name
Test status
Simulation time 23215983 ps
CPU time 0.67 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:19:02 PM PDT 24
Peak memory 191556 kb
Host smart-75534172-65a5-4e32-bdf3-0fc43cde5516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950559968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3950559968
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2944388255
Short name T548
Test name
Test status
Simulation time 43538804 ps
CPU time 2.1 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 197052 kb
Host smart-b8e01e5c-1aee-413a-a3a7-849c6d2d3505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944388255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2944388255
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2180291068
Short name T561
Test name
Test status
Simulation time 308182479 ps
CPU time 1.11 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 194828 kb
Host smart-4a38ebbb-d00c-498c-b91f-7247d82e3875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180291068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2180291068
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1515999754
Short name T472
Test name
Test status
Simulation time 24357808 ps
CPU time 0.71 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 194188 kb
Host smart-dcca10fa-1ae0-4581-a411-f552063e8c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515999754 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1515999754
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4221278943
Short name T544
Test name
Test status
Simulation time 12700194 ps
CPU time 0.63 seconds
Started Jun 28 06:18:44 PM PDT 24
Finished Jun 28 06:18:46 PM PDT 24
Peak memory 182328 kb
Host smart-92a66632-d74e-4e8f-97c1-e4f55a1b50fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221278943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4221278943
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.424384360
Short name T456
Test name
Test status
Simulation time 41713787 ps
CPU time 0.56 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 181592 kb
Host smart-7b09fa70-2a9c-47b7-9079-aa753910cd73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424384360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.424384360
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.565587726
Short name T95
Test name
Test status
Simulation time 31540610 ps
CPU time 0.67 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 191568 kb
Host smart-9fa8f207-95bc-40e0-bb48-7783641a485b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565587726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.565587726
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2474225605
Short name T498
Test name
Test status
Simulation time 815625068 ps
CPU time 2.28 seconds
Started Jun 28 06:18:44 PM PDT 24
Finished Jun 28 06:18:48 PM PDT 24
Peak memory 197152 kb
Host smart-9b7fa553-d0f0-44e7-86bd-066756d686ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474225605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2474225605
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.312530683
Short name T567
Test name
Test status
Simulation time 82979861 ps
CPU time 1.1 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 194452 kb
Host smart-d388d76c-bddf-4545-b570-55cc9f16ed30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312530683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.312530683
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3167816725
Short name T476
Test name
Test status
Simulation time 39371548 ps
CPU time 1 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:58 PM PDT 24
Peak memory 196604 kb
Host smart-37481534-bd25-42ac-8219-24759e5b1158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167816725 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3167816725
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1343859069
Short name T96
Test name
Test status
Simulation time 33462305 ps
CPU time 0.6 seconds
Started Jun 28 06:18:52 PM PDT 24
Finished Jun 28 06:19:02 PM PDT 24
Peak memory 182332 kb
Host smart-435003fb-a47c-43ff-8056-46e1606f1337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343859069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1343859069
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1954375885
Short name T474
Test name
Test status
Simulation time 14305195 ps
CPU time 0.58 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 182216 kb
Host smart-962cf176-72b1-42ec-968a-4fc092cb3d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954375885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1954375885
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.97180803
Short name T523
Test name
Test status
Simulation time 231949117 ps
CPU time 0.77 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 191276 kb
Host smart-380b4afc-f4a6-49b3-9c72-02174a7869e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97180803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_tim
er_same_csr_outstanding.97180803
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3042456735
Short name T527
Test name
Test status
Simulation time 129872511 ps
CPU time 2.64 seconds
Started Jun 28 06:18:44 PM PDT 24
Finished Jun 28 06:18:48 PM PDT 24
Peak memory 197096 kb
Host smart-ad5e2b28-8911-4893-a79f-3fbf28c24d58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042456735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3042456735
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3505555091
Short name T103
Test name
Test status
Simulation time 52063927 ps
CPU time 0.85 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 193216 kb
Host smart-935f9548-fb34-4799-89d3-97264ef5c908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505555091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3505555091
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.314308014
Short name T477
Test name
Test status
Simulation time 92735617 ps
CPU time 0.81 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 194356 kb
Host smart-ca148a57-48a4-4d59-9659-6706fd142a03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314308014 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.314308014
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1310477595
Short name T84
Test name
Test status
Simulation time 19909915 ps
CPU time 0.54 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:50 PM PDT 24
Peak memory 182280 kb
Host smart-404a1aa9-d2ab-46ac-b338-5520f8f4c700
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310477595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1310477595
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4243968703
Short name T545
Test name
Test status
Simulation time 48086674 ps
CPU time 0.58 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:56 PM PDT 24
Peak memory 182192 kb
Host smart-137042bd-70bd-4f35-9ba2-3419bf4c6cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243968703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4243968703
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3805981989
Short name T546
Test name
Test status
Simulation time 46596016 ps
CPU time 0.66 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:50 PM PDT 24
Peak memory 191036 kb
Host smart-3e6d9e87-1f2e-4fb0-aaf7-e218ebdac998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805981989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3805981989
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.300730329
Short name T535
Test name
Test status
Simulation time 209515181 ps
CPU time 1.2 seconds
Started Jun 28 06:18:52 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 196920 kb
Host smart-367709d5-d67a-4c14-ba51-f75c003a3d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300730329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.300730329
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.558200936
Short name T531
Test name
Test status
Simulation time 80942136 ps
CPU time 1.12 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 194872 kb
Host smart-683d2e33-b78b-432b-a563-f30dbd2a2e84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558200936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.558200936
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.418096960
Short name T496
Test name
Test status
Simulation time 19069117 ps
CPU time 0.63 seconds
Started Jun 28 06:18:24 PM PDT 24
Finished Jun 28 06:18:31 PM PDT 24
Peak memory 191536 kb
Host smart-4ab0db5e-c293-4df6-a79a-60a0701319ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418096960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.418096960
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4111975836
Short name T85
Test name
Test status
Simulation time 132772158 ps
CPU time 1.84 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:31 PM PDT 24
Peak memory 190636 kb
Host smart-c1a54be2-6d36-4852-9887-a1b8e1a8dff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111975836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4111975836
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.668996171
Short name T98
Test name
Test status
Simulation time 49703024 ps
CPU time 0.58 seconds
Started Jun 28 06:18:36 PM PDT 24
Finished Jun 28 06:18:38 PM PDT 24
Peak memory 182328 kb
Host smart-76e3203f-8c66-4bdb-9651-3cc6016fa103
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668996171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.668996171
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2131301353
Short name T524
Test name
Test status
Simulation time 34454700 ps
CPU time 0.9 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:28 PM PDT 24
Peak memory 196536 kb
Host smart-0ae21c01-64b3-4594-8058-9d2451de9778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131301353 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2131301353
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1490178400
Short name T89
Test name
Test status
Simulation time 42431263 ps
CPU time 0.58 seconds
Started Jun 28 06:18:17 PM PDT 24
Finished Jun 28 06:18:25 PM PDT 24
Peak memory 182316 kb
Host smart-566eb3c5-0e8e-43b6-a504-bee98933995d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490178400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1490178400
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2989568762
Short name T538
Test name
Test status
Simulation time 45597375 ps
CPU time 0.55 seconds
Started Jun 28 06:18:13 PM PDT 24
Finished Jun 28 06:18:21 PM PDT 24
Peak memory 181708 kb
Host smart-f4c9bc97-694c-42d4-94af-8396d5abe319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989568762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2989568762
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4134541962
Short name T77
Test name
Test status
Simulation time 15754379 ps
CPU time 0.67 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:29 PM PDT 24
Peak memory 191492 kb
Host smart-c00408b2-89a6-443d-8d65-9947e15c8808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134541962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4134541962
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.799835326
Short name T467
Test name
Test status
Simulation time 279286733 ps
CPU time 1.9 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:28 PM PDT 24
Peak memory 196916 kb
Host smart-e3de7612-a3a8-4063-aed4-986dff7e893b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799835326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.799835326
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3843191608
Short name T462
Test name
Test status
Simulation time 376515769 ps
CPU time 1.38 seconds
Started Jun 28 06:18:13 PM PDT 24
Finished Jun 28 06:18:22 PM PDT 24
Peak memory 195196 kb
Host smart-8ac66710-6cf3-42f9-af35-b784a71f6ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843191608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3843191608
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1332258401
Short name T458
Test name
Test status
Simulation time 142224851 ps
CPU time 0.56 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 182200 kb
Host smart-f5705d03-00aa-4a12-8c3e-779649494fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332258401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1332258401
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1170897553
Short name T470
Test name
Test status
Simulation time 104480874 ps
CPU time 0.56 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 182224 kb
Host smart-a05e5d54-139c-4c81-b00e-b55ea53299f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170897553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1170897553
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.231913427
Short name T464
Test name
Test status
Simulation time 10687566 ps
CPU time 0.54 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:50 PM PDT 24
Peak memory 181680 kb
Host smart-270fdc03-ba80-4aa0-9406-5da02cbcd11a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231913427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.231913427
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3310011931
Short name T497
Test name
Test status
Simulation time 19916949 ps
CPU time 0.54 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:19:01 PM PDT 24
Peak memory 181888 kb
Host smart-55ab3211-05f4-44c9-a7a7-ac0fc773eab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310011931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3310011931
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.542741395
Short name T539
Test name
Test status
Simulation time 14736367 ps
CPU time 0.59 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:01 PM PDT 24
Peak memory 182212 kb
Host smart-240c5c04-162e-4e1a-9e1b-556d17730471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542741395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.542741395
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3971969858
Short name T471
Test name
Test status
Simulation time 27622280 ps
CPU time 0.53 seconds
Started Jun 28 06:18:43 PM PDT 24
Finished Jun 28 06:18:44 PM PDT 24
Peak memory 181884 kb
Host smart-aba5a9b8-0116-40e2-a2a7-b4b28a1a0ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971969858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3971969858
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2927390728
Short name T511
Test name
Test status
Simulation time 11713602 ps
CPU time 0.61 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 182228 kb
Host smart-f5ca28d4-7f56-412f-be65-befb2ad1d474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927390728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2927390728
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.554976673
Short name T553
Test name
Test status
Simulation time 40390850 ps
CPU time 0.57 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 182244 kb
Host smart-dc53a168-1621-4a9d-b2e7-eba8858504dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554976673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.554976673
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1032271532
Short name T562
Test name
Test status
Simulation time 17106224 ps
CPU time 0.56 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 182132 kb
Host smart-0dbbf1bb-0394-4450-b636-617eeb5d5a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032271532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1032271532
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1578012636
Short name T520
Test name
Test status
Simulation time 38274358 ps
CPU time 0.55 seconds
Started Jun 28 06:18:46 PM PDT 24
Finished Jun 28 06:18:51 PM PDT 24
Peak memory 182180 kb
Host smart-3edc7c11-ca21-47fe-ab1b-c7da6ff1ce4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578012636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1578012636
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4096619110
Short name T86
Test name
Test status
Simulation time 18396250 ps
CPU time 0.8 seconds
Started Jun 28 06:18:36 PM PDT 24
Finished Jun 28 06:18:38 PM PDT 24
Peak memory 182304 kb
Host smart-c2153ee2-fb08-483a-a6fc-b5d154b77ec4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096619110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.4096619110
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1075421501
Short name T34
Test name
Test status
Simulation time 3029562078 ps
CPU time 2.66 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 192644 kb
Host smart-d147f2d9-cc19-42dc-bc28-a867b5a15c4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075421501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1075421501
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3643840596
Short name T33
Test name
Test status
Simulation time 14967336 ps
CPU time 0.58 seconds
Started Jun 28 06:18:28 PM PDT 24
Finished Jun 28 06:18:33 PM PDT 24
Peak memory 182328 kb
Host smart-9289f97a-e8a4-4cfa-b0d1-f22603cad5dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643840596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3643840596
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2574688810
Short name T560
Test name
Test status
Simulation time 32030559 ps
CPU time 1.53 seconds
Started Jun 28 06:18:40 PM PDT 24
Finished Jun 28 06:18:42 PM PDT 24
Peak memory 197124 kb
Host smart-9d841a3b-ae3e-4487-8f84-137f8ac28f5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574688810 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2574688810
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.773820904
Short name T503
Test name
Test status
Simulation time 11874717 ps
CPU time 0.57 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:28 PM PDT 24
Peak memory 182172 kb
Host smart-a9a04e84-45de-4ee3-8d6c-c7bdc90a4a47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773820904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.773820904
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.286470295
Short name T568
Test name
Test status
Simulation time 52683634 ps
CPU time 0.53 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:29 PM PDT 24
Peak memory 181660 kb
Host smart-2770f397-83ef-4929-8877-3315d9c763fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286470295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.286470295
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3172968161
Short name T94
Test name
Test status
Simulation time 109189590 ps
CPU time 0.83 seconds
Started Jun 28 06:18:38 PM PDT 24
Finished Jun 28 06:18:40 PM PDT 24
Peak memory 191284 kb
Host smart-4ff0b855-876d-4d63-9256-f2829877b1f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172968161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3172968161
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2016309001
Short name T480
Test name
Test status
Simulation time 165522182 ps
CPU time 3.14 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 197108 kb
Host smart-8690a3db-8b4e-4e60-8a21-c00abbeb60d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016309001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2016309001
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3327790730
Short name T32
Test name
Test status
Simulation time 293992732 ps
CPU time 1.16 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:29 PM PDT 24
Peak memory 194796 kb
Host smart-8b553355-ba8b-44a8-ab37-b9ffdd5f09e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327790730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3327790730
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2898616745
Short name T525
Test name
Test status
Simulation time 32563201 ps
CPU time 0.55 seconds
Started Jun 28 06:18:50 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 181640 kb
Host smart-dc85e8d7-262d-4946-a527-d07b625d40f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898616745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2898616745
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3198596957
Short name T483
Test name
Test status
Simulation time 39249683 ps
CPU time 0.54 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 181660 kb
Host smart-415629bf-6f03-4f7a-8df2-2cb5a308af8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198596957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3198596957
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4161604063
Short name T487
Test name
Test status
Simulation time 23062731 ps
CPU time 0.64 seconds
Started Jun 28 06:18:44 PM PDT 24
Finished Jun 28 06:18:46 PM PDT 24
Peak memory 182180 kb
Host smart-e2853409-cdb8-457b-a3bd-b3e35d7ecb94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161604063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4161604063
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3288511105
Short name T501
Test name
Test status
Simulation time 42475516 ps
CPU time 0.53 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:52 PM PDT 24
Peak memory 181892 kb
Host smart-57857ebc-52e5-4c70-ae6b-9a633287faab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288511105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3288511105
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.943863579
Short name T563
Test name
Test status
Simulation time 41340674 ps
CPU time 0.54 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:51 PM PDT 24
Peak memory 182184 kb
Host smart-04acb81a-bae0-497b-8dfa-76166402a85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943863579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.943863579
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1321823916
Short name T542
Test name
Test status
Simulation time 38170902 ps
CPU time 0.54 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:18:59 PM PDT 24
Peak memory 181728 kb
Host smart-89c4b7e6-650b-4226-b188-588dfb6b86b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321823916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1321823916
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2663609708
Short name T528
Test name
Test status
Simulation time 42781805 ps
CPU time 0.55 seconds
Started Jun 28 06:18:55 PM PDT 24
Finished Jun 28 06:19:04 PM PDT 24
Peak memory 182164 kb
Host smart-31e3501d-5933-49f2-aaf4-659731440519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663609708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2663609708
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3941831832
Short name T460
Test name
Test status
Simulation time 12970455 ps
CPU time 0.58 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 182256 kb
Host smart-8f1e0042-9a74-4ea6-8a8a-96a03b1998a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941831832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3941831832
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.940807398
Short name T533
Test name
Test status
Simulation time 19573781 ps
CPU time 0.59 seconds
Started Jun 28 06:18:43 PM PDT 24
Finished Jun 28 06:18:45 PM PDT 24
Peak memory 182156 kb
Host smart-51641579-1f5e-498f-a917-cd2f5ef7ab85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940807398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.940807398
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4147236784
Short name T490
Test name
Test status
Simulation time 142769111 ps
CPU time 0.57 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 182252 kb
Host smart-d20147de-9a5b-4fbd-8b0f-341f470fbc6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147236784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4147236784
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2218512431
Short name T514
Test name
Test status
Simulation time 18909970 ps
CPU time 0.81 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:28 PM PDT 24
Peak memory 192344 kb
Host smart-3ed000ec-67fe-43ee-88ca-56236f86b18f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218512431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2218512431
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.11892951
Short name T486
Test name
Test status
Simulation time 778740865 ps
CPU time 2.62 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 182488 kb
Host smart-eac82b8e-2a60-4510-b570-b84c49ff3382
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11892951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ba
sh.11892951
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2663174385
Short name T502
Test name
Test status
Simulation time 19250380 ps
CPU time 0.63 seconds
Started Jun 28 06:18:45 PM PDT 24
Finished Jun 28 06:18:48 PM PDT 24
Peak memory 182332 kb
Host smart-0251b09c-4977-4edd-a9c6-14b3b2e6c741
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663174385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2663174385
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1170099788
Short name T53
Test name
Test status
Simulation time 25582404 ps
CPU time 0.76 seconds
Started Jun 28 06:18:34 PM PDT 24
Finished Jun 28 06:18:36 PM PDT 24
Peak memory 194396 kb
Host smart-431f77e2-bada-46a1-9531-eea0acdd784a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170099788 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1170099788
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1741182356
Short name T87
Test name
Test status
Simulation time 13475764 ps
CPU time 0.59 seconds
Started Jun 28 06:18:22 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 182336 kb
Host smart-63fcdb13-c2a2-4537-a06d-91419ad38684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741182356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1741182356
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3391944852
Short name T493
Test name
Test status
Simulation time 14495279 ps
CPU time 0.55 seconds
Started Jun 28 06:18:30 PM PDT 24
Finished Jun 28 06:18:34 PM PDT 24
Peak memory 181816 kb
Host smart-ef8698f4-7e9d-402d-b6f4-d64486619930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391944852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3391944852
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1182294312
Short name T570
Test name
Test status
Simulation time 70836978 ps
CPU time 0.88 seconds
Started Jun 28 06:18:20 PM PDT 24
Finished Jun 28 06:18:28 PM PDT 24
Peak memory 193204 kb
Host smart-1ded33d7-43e8-4705-88d8-7005a0ee80cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182294312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1182294312
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2598641740
Short name T65
Test name
Test status
Simulation time 140227146 ps
CPU time 2.4 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:31 PM PDT 24
Peak memory 197104 kb
Host smart-6841b9c0-ae31-4d21-ba18-28e321ff6e81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598641740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2598641740
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.854695402
Short name T100
Test name
Test status
Simulation time 114855175 ps
CPU time 1.06 seconds
Started Jun 28 06:18:21 PM PDT 24
Finished Jun 28 06:18:29 PM PDT 24
Peak memory 194600 kb
Host smart-4c316816-1223-4b69-a622-2c1c173bb934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854695402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.854695402
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3929194709
Short name T529
Test name
Test status
Simulation time 13899278 ps
CPU time 0.54 seconds
Started Jun 28 06:18:47 PM PDT 24
Finished Jun 28 06:18:52 PM PDT 24
Peak memory 181648 kb
Host smart-4d52e757-2992-4e4f-a0ae-64fd8c97872d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929194709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3929194709
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2983302643
Short name T461
Test name
Test status
Simulation time 47782768 ps
CPU time 0.58 seconds
Started Jun 28 06:19:03 PM PDT 24
Finished Jun 28 06:19:09 PM PDT 24
Peak memory 182228 kb
Host smart-16d8854c-cf07-4178-b730-88d152d8dc23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983302643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2983302643
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.865276439
Short name T479
Test name
Test status
Simulation time 40990579 ps
CPU time 0.54 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:54 PM PDT 24
Peak memory 182248 kb
Host smart-69129c52-83d0-4389-bc8c-5bd6870a2fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865276439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.865276439
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.335592832
Short name T457
Test name
Test status
Simulation time 18226828 ps
CPU time 0.6 seconds
Started Jun 28 06:18:51 PM PDT 24
Finished Jun 28 06:19:00 PM PDT 24
Peak memory 182256 kb
Host smart-301745a2-3767-427b-a59d-1f8f6dd18e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335592832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.335592832
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3496421642
Short name T491
Test name
Test status
Simulation time 22232548 ps
CPU time 0.57 seconds
Started Jun 28 06:18:55 PM PDT 24
Finished Jun 28 06:19:04 PM PDT 24
Peak memory 182200 kb
Host smart-0b690ca4-a24d-411b-aaf4-02652f2e4767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496421642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3496421642
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1783609187
Short name T459
Test name
Test status
Simulation time 57698931 ps
CPU time 0.58 seconds
Started Jun 28 06:18:54 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 182348 kb
Host smart-51b8685f-b413-4236-b4c9-798864d5b4df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783609187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1783609187
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3554123666
Short name T574
Test name
Test status
Simulation time 12118313 ps
CPU time 0.55 seconds
Started Jun 28 06:18:53 PM PDT 24
Finished Jun 28 06:19:03 PM PDT 24
Peak memory 182056 kb
Host smart-7dfbec87-6939-485c-aa90-86162c72d2d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554123666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3554123666
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3661916424
Short name T522
Test name
Test status
Simulation time 14026734 ps
CPU time 0.54 seconds
Started Jun 28 06:18:49 PM PDT 24
Finished Jun 28 06:18:57 PM PDT 24
Peak memory 181552 kb
Host smart-13930e66-25c6-4e6d-a0e2-7a8d999e9808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661916424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3661916424
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3790350119
Short name T465
Test name
Test status
Simulation time 53281952 ps
CPU time 0.58 seconds
Started Jun 28 06:18:53 PM PDT 24
Finished Jun 28 06:19:02 PM PDT 24
Peak memory 182348 kb
Host smart-5a0fe571-580f-429a-b62d-060e23af8810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790350119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3790350119
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.583493478
Short name T551
Test name
Test status
Simulation time 15223341 ps
CPU time 0.53 seconds
Started Jun 28 06:18:48 PM PDT 24
Finished Jun 28 06:18:55 PM PDT 24
Peak memory 181884 kb
Host smart-1e3166a3-ec3f-4b8b-a3e9-87544ae57278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583493478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.583493478
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2017665755
Short name T505
Test name
Test status
Simulation time 56532440 ps
CPU time 0.78 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:31 PM PDT 24
Peak memory 195412 kb
Host smart-efa79383-3da6-4288-a10e-0a8b61ca2840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017665755 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2017665755
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3301560985
Short name T78
Test name
Test status
Simulation time 137165245 ps
CPU time 0.59 seconds
Started Jun 28 06:18:34 PM PDT 24
Finished Jun 28 06:18:36 PM PDT 24
Peak memory 182452 kb
Host smart-9ab92bcc-92e7-4660-b7ac-b2fb86131d0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301560985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3301560985
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2624414425
Short name T534
Test name
Test status
Simulation time 44995271 ps
CPU time 0.59 seconds
Started Jun 28 06:18:28 PM PDT 24
Finished Jun 28 06:18:33 PM PDT 24
Peak memory 182252 kb
Host smart-7476497d-aa4d-4c63-a996-5d358a5a3816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624414425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2624414425
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2118129145
Short name T549
Test name
Test status
Simulation time 20428238 ps
CPU time 0.62 seconds
Started Jun 28 06:18:25 PM PDT 24
Finished Jun 28 06:18:32 PM PDT 24
Peak memory 191012 kb
Host smart-70788e58-a349-49f1-8394-b3e05b70a3e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118129145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2118129145
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1354397774
Short name T473
Test name
Test status
Simulation time 196421920 ps
CPU time 1.96 seconds
Started Jun 28 06:18:32 PM PDT 24
Finished Jun 28 06:18:37 PM PDT 24
Peak memory 197076 kb
Host smart-04025015-0445-408c-8c89-c8e3d0b21a78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354397774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1354397774
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3457902355
Short name T104
Test name
Test status
Simulation time 306524318 ps
CPU time 1.31 seconds
Started Jun 28 06:18:33 PM PDT 24
Finished Jun 28 06:18:36 PM PDT 24
Peak memory 182960 kb
Host smart-56a19869-4ccd-4251-8921-dabbd1c6a85f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457902355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3457902355
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2502582512
Short name T518
Test name
Test status
Simulation time 67574715 ps
CPU time 0.93 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 196940 kb
Host smart-69dada52-102e-4a7e-abe7-f97b7fcf8e0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502582512 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2502582512
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3793795949
Short name T508
Test name
Test status
Simulation time 13433011 ps
CPU time 0.55 seconds
Started Jun 28 06:18:22 PM PDT 24
Finished Jun 28 06:18:29 PM PDT 24
Peak memory 182168 kb
Host smart-08c1fbe6-5b84-4cfa-888d-20715d089116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793795949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3793795949
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2043646304
Short name T566
Test name
Test status
Simulation time 17545102 ps
CPU time 0.57 seconds
Started Jun 28 06:18:22 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 182260 kb
Host smart-b1f5dcf4-666f-4f03-ad18-8282cf01dd5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043646304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2043646304
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.484484538
Short name T82
Test name
Test status
Simulation time 19288916 ps
CPU time 0.76 seconds
Started Jun 28 06:18:27 PM PDT 24
Finished Jun 28 06:18:33 PM PDT 24
Peak memory 191396 kb
Host smart-09b115c4-208b-4b5a-b9c8-05b5113d3d9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484484538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.484484538
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1174097590
Short name T40
Test name
Test status
Simulation time 164371407 ps
CPU time 2.69 seconds
Started Jun 28 06:18:26 PM PDT 24
Finished Jun 28 06:18:34 PM PDT 24
Peak memory 197112 kb
Host smart-169b1ec3-0488-415e-8b4a-3f23b6bb0f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174097590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1174097590
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3808744983
Short name T475
Test name
Test status
Simulation time 77551919 ps
CPU time 0.89 seconds
Started Jun 28 06:18:36 PM PDT 24
Finished Jun 28 06:18:38 PM PDT 24
Peak memory 193432 kb
Host smart-f645a0ca-80f0-4e58-933f-1cd954f8d0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808744983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3808744983
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1909205714
Short name T521
Test name
Test status
Simulation time 36927215 ps
CPU time 0.95 seconds
Started Jun 28 06:18:31 PM PDT 24
Finished Jun 28 06:18:35 PM PDT 24
Peak memory 196908 kb
Host smart-d26010c8-e3c7-4361-9b12-f16028efee37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909205714 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1909205714
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2804164805
Short name T541
Test name
Test status
Simulation time 88710078 ps
CPU time 0.62 seconds
Started Jun 28 06:18:35 PM PDT 24
Finished Jun 28 06:18:36 PM PDT 24
Peak memory 182332 kb
Host smart-4924d70c-404d-4e2f-8d77-5cf4ead9011a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804164805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2804164805
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2724712499
Short name T569
Test name
Test status
Simulation time 22675287 ps
CPU time 0.55 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 181704 kb
Host smart-cb9f55ec-4349-4b48-aa47-2d37610f4b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724712499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2724712499
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1539404241
Short name T97
Test name
Test status
Simulation time 129829480 ps
CPU time 0.65 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:31 PM PDT 24
Peak memory 191604 kb
Host smart-ad77b916-fd4e-41b8-94f3-907ba24db707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539404241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1539404241
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1303426242
Short name T555
Test name
Test status
Simulation time 236374885 ps
CPU time 2.02 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:32 PM PDT 24
Peak memory 197132 kb
Host smart-648af3d8-af21-4cc5-86a4-e16032d1619c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303426242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1303426242
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2046945213
Short name T550
Test name
Test status
Simulation time 112617249 ps
CPU time 1.41 seconds
Started Jun 28 06:18:22 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 195104 kb
Host smart-dd6632b3-3501-4268-879f-910fddc88ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046945213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2046945213
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2771486758
Short name T484
Test name
Test status
Simulation time 32674204 ps
CPU time 1.69 seconds
Started Jun 28 06:18:26 PM PDT 24
Finished Jun 28 06:18:34 PM PDT 24
Peak memory 197136 kb
Host smart-bbe25020-a714-4e53-97fe-2ffa2e83af80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771486758 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2771486758
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2358788558
Short name T90
Test name
Test status
Simulation time 24065332 ps
CPU time 0.64 seconds
Started Jun 28 06:18:25 PM PDT 24
Finished Jun 28 06:18:32 PM PDT 24
Peak memory 182324 kb
Host smart-72d13b29-34ad-4126-b906-235777910bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358788558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2358788558
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4150217710
Short name T576
Test name
Test status
Simulation time 12192051 ps
CPU time 0.55 seconds
Started Jun 28 06:18:37 PM PDT 24
Finished Jun 28 06:18:39 PM PDT 24
Peak memory 181696 kb
Host smart-a0d1071c-b7d1-44e6-9bf0-ad0390229650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150217710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4150217710
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3715770316
Short name T517
Test name
Test status
Simulation time 24028342 ps
CPU time 0.64 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:31 PM PDT 24
Peak memory 191644 kb
Host smart-536391d3-494d-483c-b07b-925163ea8b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715770316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3715770316
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1885187491
Short name T489
Test name
Test status
Simulation time 360982846 ps
CPU time 3.48 seconds
Started Jun 28 06:18:29 PM PDT 24
Finished Jun 28 06:18:37 PM PDT 24
Peak memory 197124 kb
Host smart-9e1be008-1adc-402b-bc7f-01b2d337e60e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885187491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1885187491
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.76229416
Short name T463
Test name
Test status
Simulation time 47245413 ps
CPU time 0.78 seconds
Started Jun 28 06:18:25 PM PDT 24
Finished Jun 28 06:18:32 PM PDT 24
Peak memory 193108 kb
Host smart-9139017e-ed68-42dc-aa67-57d17683397f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76229416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg
_err.76229416
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3697074530
Short name T510
Test name
Test status
Simulation time 17272586 ps
CPU time 0.71 seconds
Started Jun 28 06:18:35 PM PDT 24
Finished Jun 28 06:18:37 PM PDT 24
Peak memory 194176 kb
Host smart-86b7f8bf-2b09-4061-970b-a807c1c74269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697074530 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3697074530
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3356102972
Short name T83
Test name
Test status
Simulation time 18137702 ps
CPU time 0.6 seconds
Started Jun 28 06:18:35 PM PDT 24
Finished Jun 28 06:18:36 PM PDT 24
Peak memory 182332 kb
Host smart-2b015ae0-3e1e-4c6b-ab8d-8355d7da5e6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356102972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3356102972
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.696079101
Short name T466
Test name
Test status
Simulation time 42761395 ps
CPU time 0.56 seconds
Started Jun 28 06:18:28 PM PDT 24
Finished Jun 28 06:18:33 PM PDT 24
Peak memory 182252 kb
Host smart-50025e9d-384e-4e2c-b720-0e212bfff030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696079101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.696079101
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4029561468
Short name T81
Test name
Test status
Simulation time 85348683 ps
CPU time 0.71 seconds
Started Jun 28 06:18:27 PM PDT 24
Finished Jun 28 06:18:33 PM PDT 24
Peak memory 191300 kb
Host smart-4094e6e7-196c-4c70-9d6e-3e24764c5cd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029561468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.4029561468
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1184967272
Short name T536
Test name
Test status
Simulation time 132627666 ps
CPU time 1.39 seconds
Started Jun 28 06:18:26 PM PDT 24
Finished Jun 28 06:18:33 PM PDT 24
Peak memory 197108 kb
Host smart-3fce3f66-79a3-45de-a4b3-8dfca769962e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184967272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1184967272
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3500877980
Short name T54
Test name
Test status
Simulation time 46104179 ps
CPU time 0.88 seconds
Started Jun 28 06:18:23 PM PDT 24
Finished Jun 28 06:18:30 PM PDT 24
Peak memory 193144 kb
Host smart-6b911227-c2b2-490d-b424-a15d12ab2120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500877980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3500877980
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1042901704
Short name T155
Test name
Test status
Simulation time 424140232126 ps
CPU time 233.02 seconds
Started Jun 28 07:18:16 PM PDT 24
Finished Jun 28 07:22:20 PM PDT 24
Peak memory 183156 kb
Host smart-485dedb5-fba6-4a8d-9558-852d45099b9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042901704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1042901704
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2471168999
Short name T394
Test name
Test status
Simulation time 32622142119 ps
CPU time 45.63 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:19:14 PM PDT 24
Peak memory 183180 kb
Host smart-9e3ba138-1f7f-4dd1-bb90-6d711cb3e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471168999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2471168999
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1210562264
Short name T214
Test name
Test status
Simulation time 434962449113 ps
CPU time 1051.39 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:37:04 PM PDT 24
Peak memory 190740 kb
Host smart-75f1fd8c-fe8d-49b3-904d-aa6cb2746773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210562264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1210562264
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.3900216823
Short name T36
Test name
Test status
Simulation time 74831619345 ps
CPU time 602.93 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:29:32 PM PDT 24
Peak memory 213636 kb
Host smart-4bcefd33-ff50-4666-a63b-a7ab64614c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900216823 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.3900216823
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1979628602
Short name T188
Test name
Test status
Simulation time 309781522300 ps
CPU time 71.88 seconds
Started Jun 28 07:19:03 PM PDT 24
Finished Jun 28 07:20:37 PM PDT 24
Peak memory 183164 kb
Host smart-7c8a08a2-6027-4116-b6ae-87dcd4a31d70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979628602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1979628602
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.348267734
Short name T372
Test name
Test status
Simulation time 117344940626 ps
CPU time 148.88 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:21:59 PM PDT 24
Peak memory 183168 kb
Host smart-8b4835a6-7e58-4aa0-bac9-874af427509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348267734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.348267734
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2585882756
Short name T164
Test name
Test status
Simulation time 79848071921 ps
CPU time 51.02 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:20:23 PM PDT 24
Peak memory 191364 kb
Host smart-8f092901-9fbb-4cec-8f21-70812ca9844e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585882756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2585882756
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3318903887
Short name T398
Test name
Test status
Simulation time 6366912122 ps
CPU time 17.44 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:19:46 PM PDT 24
Peak memory 183116 kb
Host smart-b0d2a3ef-65e5-45f6-9d25-7f6455ff4bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318903887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3318903887
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3312469700
Short name T21
Test name
Test status
Simulation time 732731550 ps
CPU time 0.86 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:19:34 PM PDT 24
Peak memory 212908 kb
Host smart-76f5321a-01be-45ca-92a1-653f9645e581
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312469700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3312469700
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1651139890
Short name T433
Test name
Test status
Simulation time 511533529648 ps
CPU time 262.32 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:23:52 PM PDT 24
Peak memory 183160 kb
Host smart-3fb57a6d-ba4a-41fa-adb2-70dcfe9aa1a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651139890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1651139890
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2629265358
Short name T370
Test name
Test status
Simulation time 60050404783 ps
CPU time 44.47 seconds
Started Jun 28 07:19:04 PM PDT 24
Finished Jun 28 07:20:12 PM PDT 24
Peak memory 183172 kb
Host smart-4d2fe139-b9e9-4684-b182-9e256c908015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629265358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2629265358
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2231752356
Short name T319
Test name
Test status
Simulation time 95526655824 ps
CPU time 1689.85 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:47:40 PM PDT 24
Peak memory 183188 kb
Host smart-e95de6dc-bd0a-4fd2-a442-1a394cebe886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231752356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2231752356
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2782624731
Short name T175
Test name
Test status
Simulation time 789211232156 ps
CPU time 363.98 seconds
Started Jun 28 07:21:45 PM PDT 24
Finished Jun 28 07:27:53 PM PDT 24
Peak memory 191356 kb
Host smart-d29b07fd-9d6b-43fa-9a37-2797592c81be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782624731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2782624731
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.523697990
Short name T278
Test name
Test status
Simulation time 102261464965 ps
CPU time 1590.46 seconds
Started Jun 28 07:21:43 PM PDT 24
Finished Jun 28 07:48:19 PM PDT 24
Peak memory 191368 kb
Host smart-48c00173-8a7d-4106-92fc-31048b4a3512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523697990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.523697990
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2912591545
Short name T350
Test name
Test status
Simulation time 747995775026 ps
CPU time 400.71 seconds
Started Jun 28 07:21:44 PM PDT 24
Finished Jun 28 07:28:29 PM PDT 24
Peak memory 191364 kb
Host smart-8b62bf8e-a75a-4c61-b29d-7db94a547a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912591545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2912591545
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.539407447
Short name T418
Test name
Test status
Simulation time 277855622748 ps
CPU time 151.19 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:22:04 PM PDT 24
Peak memory 183172 kb
Host smart-8ef3dc05-c070-42a5-b874-d5c2f2c9729d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539407447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.539407447
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.411093613
Short name T409
Test name
Test status
Simulation time 276450509338 ps
CPU time 213.15 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:23:08 PM PDT 24
Peak memory 183036 kb
Host smart-5d15dfd7-57cd-44c5-b901-bf03abf6eaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411093613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.411093613
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/110.rv_timer_random.345835245
Short name T191
Test name
Test status
Simulation time 339636082678 ps
CPU time 1893.55 seconds
Started Jun 28 07:21:39 PM PDT 24
Finished Jun 28 07:53:14 PM PDT 24
Peak memory 191364 kb
Host smart-265c3340-8289-4052-8adc-5f4f9cf8f718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345835245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.345835245
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3924352109
Short name T329
Test name
Test status
Simulation time 260649136736 ps
CPU time 349.63 seconds
Started Jun 28 07:21:41 PM PDT 24
Finished Jun 28 07:27:35 PM PDT 24
Peak memory 191344 kb
Host smart-6d0cb160-f67a-4e11-9786-bb9b9befbc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924352109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3924352109
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.962229051
Short name T452
Test name
Test status
Simulation time 91224496945 ps
CPU time 80.68 seconds
Started Jun 28 07:21:41 PM PDT 24
Finished Jun 28 07:23:06 PM PDT 24
Peak memory 183172 kb
Host smart-7fb51df8-0118-4aec-b964-a63e240e4a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962229051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.962229051
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2761646274
Short name T12
Test name
Test status
Simulation time 113523827638 ps
CPU time 1497 seconds
Started Jun 28 07:21:42 PM PDT 24
Finished Jun 28 07:46:44 PM PDT 24
Peak memory 191356 kb
Host smart-63a31ca9-d4dc-4146-9a38-0376c8b4f143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761646274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2761646274
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2797484946
Short name T62
Test name
Test status
Simulation time 558690675209 ps
CPU time 550.17 seconds
Started Jun 28 07:21:43 PM PDT 24
Finished Jun 28 07:30:58 PM PDT 24
Peak memory 191332 kb
Host smart-5ff68414-9519-45e3-ad69-7735df5f3db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797484946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2797484946
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1424138666
Short name T287
Test name
Test status
Simulation time 289710332803 ps
CPU time 165.06 seconds
Started Jun 28 07:21:42 PM PDT 24
Finished Jun 28 07:24:31 PM PDT 24
Peak memory 191364 kb
Host smart-9f0a8d7b-84d1-446d-b835-53f1ed7a093a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424138666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1424138666
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1722837701
Short name T182
Test name
Test status
Simulation time 2047252974604 ps
CPU time 1094.29 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:37:48 PM PDT 24
Peak memory 183148 kb
Host smart-a2845475-e2da-4a1d-9bf2-486955350747
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722837701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1722837701
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.800828479
Short name T395
Test name
Test status
Simulation time 193947560972 ps
CPU time 147.04 seconds
Started Jun 28 07:19:04 PM PDT 24
Finished Jun 28 07:21:53 PM PDT 24
Peak memory 183148 kb
Host smart-954b31a2-3c48-4284-ac77-a8d39c3e5229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800828479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.800828479
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4209183746
Short name T148
Test name
Test status
Simulation time 1840530868584 ps
CPU time 705.98 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:31:21 PM PDT 24
Peak memory 191224 kb
Host smart-606ce818-3191-4d4c-b84f-a2d123bd3a4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209183746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4209183746
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.3913040009
Short name T450
Test name
Test status
Simulation time 314529838377 ps
CPU time 269.51 seconds
Started Jun 28 07:21:41 PM PDT 24
Finished Jun 28 07:26:15 PM PDT 24
Peak memory 191360 kb
Host smart-7c1ebb17-97d9-489f-af81-766f42d3f75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913040009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3913040009
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1889700893
Short name T323
Test name
Test status
Simulation time 267724626634 ps
CPU time 204.29 seconds
Started Jun 28 07:21:44 PM PDT 24
Finished Jun 28 07:25:13 PM PDT 24
Peak memory 191356 kb
Host smart-c9b29f1d-1ac2-4a97-90cc-28d8053b2604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889700893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1889700893
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3457014317
Short name T230
Test name
Test status
Simulation time 174772301937 ps
CPU time 1426.33 seconds
Started Jun 28 07:21:41 PM PDT 24
Finished Jun 28 07:45:31 PM PDT 24
Peak memory 194828 kb
Host smart-c3d2fa80-8c52-4f27-b2dd-771d79576b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457014317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3457014317
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3125637840
Short name T207
Test name
Test status
Simulation time 646581161180 ps
CPU time 817.19 seconds
Started Jun 28 07:21:41 PM PDT 24
Finished Jun 28 07:35:23 PM PDT 24
Peak memory 191312 kb
Host smart-50d64ee6-48bd-4801-838d-6f6218240e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125637840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3125637840
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3890496806
Short name T293
Test name
Test status
Simulation time 2999500788 ps
CPU time 3.39 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:22:03 PM PDT 24
Peak memory 183164 kb
Host smart-e3355798-5a66-4de2-9e20-393d67220fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890496806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3890496806
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2310335108
Short name T400
Test name
Test status
Simulation time 645689803893 ps
CPU time 789.89 seconds
Started Jun 28 07:22:02 PM PDT 24
Finished Jun 28 07:35:15 PM PDT 24
Peak memory 191356 kb
Host smart-3201dc1a-4789-4164-b5bb-7c1a1e1b1a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310335108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2310335108
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4043481722
Short name T348
Test name
Test status
Simulation time 473189987271 ps
CPU time 286 seconds
Started Jun 28 07:21:56 PM PDT 24
Finished Jun 28 07:26:45 PM PDT 24
Peak memory 191356 kb
Host smart-70d21a29-19aa-47e9-94d2-e20e488a078c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043481722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4043481722
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.623818000
Short name T445
Test name
Test status
Simulation time 198639786022 ps
CPU time 55.56 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:22:55 PM PDT 24
Peak memory 183164 kb
Host smart-67ab54e1-968d-4d38-9e4e-7b5c94df0af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623818000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.623818000
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2118265344
Short name T341
Test name
Test status
Simulation time 172791021376 ps
CPU time 43.67 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:20:18 PM PDT 24
Peak memory 183084 kb
Host smart-61b3b8d8-9277-4eff-9ca3-10c4e1e024d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118265344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2118265344
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.269592206
Short name T374
Test name
Test status
Simulation time 267890622261 ps
CPU time 105.85 seconds
Started Jun 28 07:19:14 PM PDT 24
Finished Jun 28 07:21:23 PM PDT 24
Peak memory 183180 kb
Host smart-b104ecd9-3c58-43e5-8a50-b2a276f82881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269592206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.269592206
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2274343453
Short name T301
Test name
Test status
Simulation time 26317041684 ps
CPU time 23.44 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:19:58 PM PDT 24
Peak memory 191388 kb
Host smart-3a765b36-3eb1-4104-8037-f4e84fd83ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274343453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2274343453
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3695524194
Short name T71
Test name
Test status
Simulation time 21203157 ps
CPU time 0.57 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:19:35 PM PDT 24
Peak memory 183004 kb
Host smart-c68e6635-49f1-4ab9-904b-6b334cadc1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695524194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3695524194
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.1795719562
Short name T114
Test name
Test status
Simulation time 54717530513 ps
CPU time 89.5 seconds
Started Jun 28 07:22:01 PM PDT 24
Finished Jun 28 07:23:33 PM PDT 24
Peak memory 183140 kb
Host smart-91ee3130-902f-48b4-96d4-3e92ba07fe1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795719562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1795719562
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.836926435
Short name T425
Test name
Test status
Simulation time 119607967274 ps
CPU time 267.52 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:26:27 PM PDT 24
Peak memory 183100 kb
Host smart-c614a94a-9228-428e-89f7-464e801bf7ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836926435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.836926435
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3641270420
Short name T345
Test name
Test status
Simulation time 129477422794 ps
CPU time 54.06 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:22:53 PM PDT 24
Peak memory 183156 kb
Host smart-f1551b1e-addb-4a92-9c40-912474f5dc54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641270420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3641270420
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.65925864
Short name T265
Test name
Test status
Simulation time 214738870528 ps
CPU time 174.35 seconds
Started Jun 28 07:22:03 PM PDT 24
Finished Jun 28 07:25:00 PM PDT 24
Peak memory 191356 kb
Host smart-4de44eac-491b-48f1-b809-1ab7f6961c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65925864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.65925864
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1707925873
Short name T166
Test name
Test status
Simulation time 45304313786 ps
CPU time 79.87 seconds
Started Jun 28 07:21:57 PM PDT 24
Finished Jun 28 07:23:20 PM PDT 24
Peak memory 183164 kb
Host smart-09978ae5-3d1e-4c03-a14c-952d6943d626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707925873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1707925873
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.592274752
Short name T158
Test name
Test status
Simulation time 360199036882 ps
CPU time 291.44 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:24:26 PM PDT 24
Peak memory 183168 kb
Host smart-ba0bf701-1d8b-42e2-8f4b-c3d9ee1ccbc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592274752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.592274752
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2930225819
Short name T434
Test name
Test status
Simulation time 69088657744 ps
CPU time 86.55 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:21:01 PM PDT 24
Peak memory 183180 kb
Host smart-410830ae-06cf-4e17-baaf-42f0a739e6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930225819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2930225819
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.688100644
Short name T236
Test name
Test status
Simulation time 59390633918 ps
CPU time 45.8 seconds
Started Jun 28 07:18:47 PM PDT 24
Finished Jun 28 07:19:33 PM PDT 24
Peak memory 183072 kb
Host smart-48f048e9-f4a2-4028-a388-011d5c5ef48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688100644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.688100644
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.409221290
Short name T443
Test name
Test status
Simulation time 193743374 ps
CPU time 0.7 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:19:34 PM PDT 24
Peak memory 183144 kb
Host smart-28e85a00-712c-4dfa-9276-f5a015929bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409221290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.409221290
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2251124242
Short name T69
Test name
Test status
Simulation time 2546427949673 ps
CPU time 830.19 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:33:21 PM PDT 24
Peak memory 191360 kb
Host smart-b5ababb6-f6c2-4c61-ae6b-72f5f95e79b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251124242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2251124242
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/143.rv_timer_random.2967338637
Short name T165
Test name
Test status
Simulation time 636016924934 ps
CPU time 373.36 seconds
Started Jun 28 07:22:20 PM PDT 24
Finished Jun 28 07:28:38 PM PDT 24
Peak memory 191364 kb
Host smart-a4608d20-4c8c-44be-ae5f-6b058cbb35b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967338637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2967338637
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.811497585
Short name T4
Test name
Test status
Simulation time 116218101664 ps
CPU time 504.85 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:30:49 PM PDT 24
Peak memory 191340 kb
Host smart-026035ed-16ef-4782-8e89-995af8065737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811497585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.811497585
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2331502149
Short name T24
Test name
Test status
Simulation time 59010568688 ps
CPU time 109.39 seconds
Started Jun 28 07:22:22 PM PDT 24
Finished Jun 28 07:24:16 PM PDT 24
Peak memory 191356 kb
Host smart-908d3c04-163a-4dd3-9f77-b2eb9e92097b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331502149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2331502149
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3932080137
Short name T307
Test name
Test status
Simulation time 204019718238 ps
CPU time 234.54 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:26:16 PM PDT 24
Peak memory 191344 kb
Host smart-49c6331c-b92e-4710-aedb-15e30ec37f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932080137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3932080137
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.270282391
Short name T163
Test name
Test status
Simulation time 68084249884 ps
CPU time 124.16 seconds
Started Jun 28 07:22:18 PM PDT 24
Finished Jun 28 07:24:23 PM PDT 24
Peak memory 191360 kb
Host smart-6877c50e-4408-4123-a08d-226105f848dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270282391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.270282391
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.4206848353
Short name T327
Test name
Test status
Simulation time 30596274529 ps
CPU time 64.56 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:23:28 PM PDT 24
Peak memory 191372 kb
Host smart-3aa5b1a0-6a5c-467a-bd4e-c011ddd9f00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206848353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.4206848353
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4146092943
Short name T198
Test name
Test status
Simulation time 127092313810 ps
CPU time 109.87 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:21:24 PM PDT 24
Peak memory 183072 kb
Host smart-d27777e9-dc48-4cdd-b556-0736c0c253c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146092943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.4146092943
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3133445721
Short name T414
Test name
Test status
Simulation time 357717313240 ps
CPU time 242.52 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:23:37 PM PDT 24
Peak memory 183296 kb
Host smart-5c0f422c-9e11-4565-9008-fdd0248fd259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133445721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3133445721
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.629194447
Short name T146
Test name
Test status
Simulation time 159754597703 ps
CPU time 528.28 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:28:21 PM PDT 24
Peak memory 191276 kb
Host smart-6208a221-24df-4285-9d44-3264720fea60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629194447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.629194447
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3023658270
Short name T107
Test name
Test status
Simulation time 108222276085 ps
CPU time 47.25 seconds
Started Jun 28 07:19:12 PM PDT 24
Finished Jun 28 07:20:24 PM PDT 24
Peak memory 191380 kb
Host smart-d1d9a385-6114-4f09-9b8a-71d1e9d9b462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023658270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3023658270
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1944318904
Short name T306
Test name
Test status
Simulation time 188786325401 ps
CPU time 146.7 seconds
Started Jun 28 07:19:12 PM PDT 24
Finished Jun 28 07:22:03 PM PDT 24
Peak memory 194428 kb
Host smart-3927e397-6265-4e56-b58d-284d3a257e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944318904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1944318904
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1239880874
Short name T189
Test name
Test status
Simulation time 211887903375 ps
CPU time 443.75 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:29:45 PM PDT 24
Peak memory 191312 kb
Host smart-13d83ebf-c6d6-4e67-9066-495fc221f33f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239880874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1239880874
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.4113850198
Short name T264
Test name
Test status
Simulation time 102951119071 ps
CPU time 185.22 seconds
Started Jun 28 07:22:18 PM PDT 24
Finished Jun 28 07:25:26 PM PDT 24
Peak memory 194888 kb
Host smart-b774bc3a-2710-4e20-a883-c784e838f321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113850198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4113850198
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.933411921
Short name T392
Test name
Test status
Simulation time 100476120088 ps
CPU time 34.72 seconds
Started Jun 28 07:22:18 PM PDT 24
Finished Jun 28 07:22:55 PM PDT 24
Peak memory 183164 kb
Host smart-47fa0894-35ea-4a2a-b1f7-9d50f1a72e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933411921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.933411921
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1046339212
Short name T284
Test name
Test status
Simulation time 193156506971 ps
CPU time 298.61 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:27:21 PM PDT 24
Peak memory 191328 kb
Host smart-53ccba8d-9475-47bc-a1ea-da3a8c349788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046339212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1046339212
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1103735720
Short name T14
Test name
Test status
Simulation time 24076329353 ps
CPU time 35.92 seconds
Started Jun 28 07:22:20 PM PDT 24
Finished Jun 28 07:23:00 PM PDT 24
Peak memory 183160 kb
Host smart-26fcedfd-3f22-4220-b9ab-3f75f7da84e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103735720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1103735720
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2990554586
Short name T273
Test name
Test status
Simulation time 391839525446 ps
CPU time 169.2 seconds
Started Jun 28 07:22:21 PM PDT 24
Finished Jun 28 07:25:16 PM PDT 24
Peak memory 191356 kb
Host smart-4273b06a-22a4-4de9-be6d-570f9e2d71ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990554586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2990554586
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3881390504
Short name T328
Test name
Test status
Simulation time 13202013870 ps
CPU time 467.73 seconds
Started Jun 28 07:22:18 PM PDT 24
Finished Jun 28 07:30:07 PM PDT 24
Peak memory 183136 kb
Host smart-0648de60-cd17-43fe-b76c-2d48c9c4fbdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881390504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3881390504
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2507556601
Short name T346
Test name
Test status
Simulation time 127247849431 ps
CPU time 98.47 seconds
Started Jun 28 07:22:20 PM PDT 24
Finished Jun 28 07:24:03 PM PDT 24
Peak memory 191352 kb
Host smart-b0b5bfe6-af6c-440c-9d95-c04b63d323ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507556601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2507556601
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1265025112
Short name T209
Test name
Test status
Simulation time 474971623798 ps
CPU time 412.52 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:26:24 PM PDT 24
Peak memory 183156 kb
Host smart-8e879c92-b100-4275-b965-58f4ba1b4b2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265025112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1265025112
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2630853120
Short name T368
Test name
Test status
Simulation time 83564421672 ps
CPU time 120.83 seconds
Started Jun 28 07:19:13 PM PDT 24
Finished Jun 28 07:21:38 PM PDT 24
Peak memory 183172 kb
Host smart-33248604-3188-4f16-a97f-fb74e9531df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630853120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2630853120
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1702771803
Short name T227
Test name
Test status
Simulation time 118470327697 ps
CPU time 51.18 seconds
Started Jun 28 07:18:54 PM PDT 24
Finished Jun 28 07:20:00 PM PDT 24
Peak memory 191340 kb
Host smart-1eaad6f9-ef6a-4e08-9fff-3f612e7ab7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702771803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1702771803
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2848228788
Short name T208
Test name
Test status
Simulation time 993999998671 ps
CPU time 711.47 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:34:15 PM PDT 24
Peak memory 191500 kb
Host smart-9b9ab5f1-fac6-418d-8304-9939ff020359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848228788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2848228788
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2062843606
Short name T275
Test name
Test status
Simulation time 63709103189 ps
CPU time 113.83 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:24:16 PM PDT 24
Peak memory 191364 kb
Host smart-e7554a32-c43c-4350-9eb7-866dc8029730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062843606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2062843606
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.4057142326
Short name T200
Test name
Test status
Simulation time 465914452537 ps
CPU time 1287.15 seconds
Started Jun 28 07:22:19 PM PDT 24
Finished Jun 28 07:43:51 PM PDT 24
Peak memory 191276 kb
Host smart-5265718d-6978-400d-8c12-54a3f728bfed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057142326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4057142326
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3150542366
Short name T270
Test name
Test status
Simulation time 37391856869 ps
CPU time 61.42 seconds
Started Jun 28 07:22:20 PM PDT 24
Finished Jun 28 07:23:26 PM PDT 24
Peak memory 191284 kb
Host smart-bbc2edf3-b9a0-41a8-846a-94d0bf55f6c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150542366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3150542366
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.925384835
Short name T244
Test name
Test status
Simulation time 199739812622 ps
CPU time 202.24 seconds
Started Jun 28 07:22:21 PM PDT 24
Finished Jun 28 07:25:48 PM PDT 24
Peak memory 191360 kb
Host smart-f3a57f29-3fb4-4e63-a9ab-aa09786bb6d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925384835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.925384835
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.387598335
Short name T76
Test name
Test status
Simulation time 133879348094 ps
CPU time 559.86 seconds
Started Jun 28 07:22:53 PM PDT 24
Finished Jun 28 07:32:16 PM PDT 24
Peak memory 191376 kb
Host smart-3b3f6cbd-344b-4d58-b6bf-712f1f0022cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387598335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.387598335
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.560728266
Short name T397
Test name
Test status
Simulation time 62868422084 ps
CPU time 29.23 seconds
Started Jun 28 07:22:53 PM PDT 24
Finished Jun 28 07:23:25 PM PDT 24
Peak memory 183264 kb
Host smart-f95e3897-8ea3-42b0-90cb-a5e0b3018fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560728266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.560728266
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1900486269
Short name T403
Test name
Test status
Simulation time 75008692811 ps
CPU time 91.94 seconds
Started Jun 28 07:19:12 PM PDT 24
Finished Jun 28 07:21:09 PM PDT 24
Peak memory 183164 kb
Host smart-9e9d2ea7-7e97-4c77-be97-4d985418a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900486269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1900486269
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3510672613
Short name T2
Test name
Test status
Simulation time 89731648774 ps
CPU time 53.28 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:20:22 PM PDT 24
Peak memory 183080 kb
Host smart-0ce0af03-fb9b-4262-880c-721bc84a3eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510672613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3510672613
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.309635483
Short name T382
Test name
Test status
Simulation time 138506518 ps
CPU time 0.76 seconds
Started Jun 28 07:19:14 PM PDT 24
Finished Jun 28 07:19:38 PM PDT 24
Peak memory 183020 kb
Host smart-8d804271-4102-4fdc-9d4e-7394a7077029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309635483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.309635483
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2519882907
Short name T203
Test name
Test status
Simulation time 214447889629 ps
CPU time 305.92 seconds
Started Jun 28 07:19:13 PM PDT 24
Finished Jun 28 07:24:43 PM PDT 24
Peak memory 191360 kb
Host smart-fcba8bcf-aaf7-489f-a377-0a991172b99f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519882907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2519882907
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.3153962025
Short name T43
Test name
Test status
Simulation time 110031468953 ps
CPU time 65.22 seconds
Started Jun 28 07:22:55 PM PDT 24
Finished Jun 28 07:24:04 PM PDT 24
Peak memory 183160 kb
Host smart-6f110b6e-b8c5-41fc-be68-eb286a61c14f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153962025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3153962025
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.4185659292
Short name T6
Test name
Test status
Simulation time 117062516469 ps
CPU time 199.38 seconds
Started Jun 28 07:22:53 PM PDT 24
Finished Jun 28 07:26:15 PM PDT 24
Peak memory 191364 kb
Host smart-2d9dc8bf-86ec-4505-91bb-7c69c4e8380f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185659292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.4185659292
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1369373378
Short name T336
Test name
Test status
Simulation time 86299520674 ps
CPU time 113.8 seconds
Started Jun 28 07:22:55 PM PDT 24
Finished Jun 28 07:24:52 PM PDT 24
Peak memory 191364 kb
Host smart-8c093976-b639-4f59-ae3f-fa1fa313d95f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369373378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1369373378
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.326003725
Short name T285
Test name
Test status
Simulation time 183090963770 ps
CPU time 66.87 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:24:05 PM PDT 24
Peak memory 183044 kb
Host smart-bc43b736-814b-4885-9616-5749be0cf433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326003725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.326003725
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4040923016
Short name T282
Test name
Test status
Simulation time 78120284875 ps
CPU time 58.08 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:23:56 PM PDT 24
Peak memory 183168 kb
Host smart-27cefeb9-4187-481b-b6b6-6386578fdbbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040923016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4040923016
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.974414000
Short name T286
Test name
Test status
Simulation time 407237650098 ps
CPU time 691.19 seconds
Started Jun 28 07:19:13 PM PDT 24
Finished Jun 28 07:31:09 PM PDT 24
Peak memory 183164 kb
Host smart-a8ab8053-ebb5-483e-b684-6d2a9a3edad0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974414000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.974414000
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2960175764
Short name T386
Test name
Test status
Simulation time 99111744804 ps
CPU time 69.38 seconds
Started Jun 28 07:19:14 PM PDT 24
Finished Jun 28 07:20:46 PM PDT 24
Peak memory 183172 kb
Host smart-9f7af8c9-dfd9-4b50-8e1e-9f9835f607ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960175764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2960175764
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.202219791
Short name T25
Test name
Test status
Simulation time 731233194 ps
CPU time 1.48 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:19:34 PM PDT 24
Peak memory 183036 kb
Host smart-0b7fca64-23e8-468e-90f1-b17497ce50da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202219791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.202219791
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2574152828
Short name T390
Test name
Test status
Simulation time 63771103580 ps
CPU time 44.47 seconds
Started Jun 28 07:19:13 PM PDT 24
Finished Jun 28 07:20:22 PM PDT 24
Peak memory 194708 kb
Host smart-8b72943c-1e4f-43ad-87fc-6aec4897828a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574152828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2574152828
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.335682538
Short name T45
Test name
Test status
Simulation time 51729254629 ps
CPU time 255.49 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:27:13 PM PDT 24
Peak memory 183168 kb
Host smart-09515946-1d20-477f-8a33-6f58a6ab686e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335682538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.335682538
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2081644142
Short name T180
Test name
Test status
Simulation time 423083095970 ps
CPU time 198.27 seconds
Started Jun 28 07:22:56 PM PDT 24
Finished Jun 28 07:26:18 PM PDT 24
Peak memory 191352 kb
Host smart-bdeca70b-eb7a-4277-8b80-63d35822517c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081644142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2081644142
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.175388995
Short name T184
Test name
Test status
Simulation time 241264868371 ps
CPU time 123.05 seconds
Started Jun 28 07:22:54 PM PDT 24
Finished Jun 28 07:25:01 PM PDT 24
Peak memory 191280 kb
Host smart-c523aa31-867a-42d8-9f42-3207f90fc969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175388995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.175388995
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2015249752
Short name T139
Test name
Test status
Simulation time 215725719595 ps
CPU time 564.31 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:32:55 PM PDT 24
Peak memory 191364 kb
Host smart-30adac11-f464-4023-874f-7ed613c83c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015249752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2015249752
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2946197252
Short name T135
Test name
Test status
Simulation time 152145770249 ps
CPU time 104.48 seconds
Started Jun 28 07:23:34 PM PDT 24
Finished Jun 28 07:25:26 PM PDT 24
Peak memory 191356 kb
Host smart-36d40bbb-7721-4b57-a382-581fdc46aede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946197252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2946197252
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.775500382
Short name T429
Test name
Test status
Simulation time 326650923979 ps
CPU time 456.2 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:27:09 PM PDT 24
Peak memory 183032 kb
Host smart-c4aff0ad-a6d0-449a-b3fc-d2391ebae819
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775500382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.775500382
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2121161968
Short name T422
Test name
Test status
Simulation time 171686695880 ps
CPU time 223.21 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:23:18 PM PDT 24
Peak memory 183176 kb
Host smart-094a6592-da0f-4f85-9483-4b76614d2b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121161968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2121161968
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.4026648603
Short name T279
Test name
Test status
Simulation time 306426742683 ps
CPU time 218.43 seconds
Started Jun 28 07:19:13 PM PDT 24
Finished Jun 28 07:23:15 PM PDT 24
Peak memory 191360 kb
Host smart-67659872-b8c8-4e97-8659-5773915ed12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026648603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.4026648603
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2464152614
Short name T406
Test name
Test status
Simulation time 64038993573 ps
CPU time 95.67 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:21:08 PM PDT 24
Peak memory 194704 kb
Host smart-f9322ed3-bc11-468a-a7c5-e2ec8d3d806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464152614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2464152614
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.3784126341
Short name T330
Test name
Test status
Simulation time 575668828082 ps
CPU time 387.48 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:30:00 PM PDT 24
Peak memory 191304 kb
Host smart-0a23da66-42e8-4329-9971-153bf5f57064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784126341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3784126341
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1452736296
Short name T258
Test name
Test status
Simulation time 93193113334 ps
CPU time 160.22 seconds
Started Jun 28 07:23:33 PM PDT 24
Finished Jun 28 07:26:21 PM PDT 24
Peak memory 193760 kb
Host smart-0ba3725d-6bac-4e8a-9a85-6f92a65fbb09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452736296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1452736296
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3397419621
Short name T215
Test name
Test status
Simulation time 141404398986 ps
CPU time 114.35 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:25:25 PM PDT 24
Peak memory 191364 kb
Host smart-321eaccd-413b-4d8b-b935-5f86076159fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397419621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3397419621
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1172885613
Short name T63
Test name
Test status
Simulation time 53989036037 ps
CPU time 86.81 seconds
Started Jun 28 07:23:32 PM PDT 24
Finished Jun 28 07:25:05 PM PDT 24
Peak memory 191372 kb
Host smart-bda684fa-f618-4993-93f2-d3ccbce54e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172885613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1172885613
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.996953557
Short name T324
Test name
Test status
Simulation time 279636888400 ps
CPU time 1598.95 seconds
Started Jun 28 07:23:04 PM PDT 24
Finished Jun 28 07:49:46 PM PDT 24
Peak memory 191368 kb
Host smart-597b99af-8606-4d49-ab91-eed3d3e92f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996953557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.996953557
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.4135357302
Short name T332
Test name
Test status
Simulation time 31877935167 ps
CPU time 65.9 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:24:36 PM PDT 24
Peak memory 191316 kb
Host smart-daef357c-2c49-462b-8f5f-26d422b72d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135357302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4135357302
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1993867320
Short name T225
Test name
Test status
Simulation time 433711458348 ps
CPU time 349.19 seconds
Started Jun 28 07:23:27 PM PDT 24
Finished Jun 28 07:29:19 PM PDT 24
Peak memory 191364 kb
Host smart-95ef06b0-fe71-4cdc-bc58-087608527719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993867320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1993867320
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4053658355
Short name T206
Test name
Test status
Simulation time 16818015238 ps
CPU time 133.36 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:25:45 PM PDT 24
Peak memory 183164 kb
Host smart-c876ac01-2686-4973-bc32-96a4ad6c6cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053658355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4053658355
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3476080289
Short name T277
Test name
Test status
Simulation time 213171141546 ps
CPU time 159.29 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:26:09 PM PDT 24
Peak memory 194912 kb
Host smart-95df3658-dcfe-4136-8888-2c43b522c918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476080289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3476080289
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.579668993
Short name T262
Test name
Test status
Simulation time 703176811983 ps
CPU time 516.34 seconds
Started Jun 28 07:19:03 PM PDT 24
Finished Jun 28 07:28:01 PM PDT 24
Peak memory 183148 kb
Host smart-804ccd3e-44aa-4ed6-ad43-a6b666d75974
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579668993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.579668993
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.991876400
Short name T393
Test name
Test status
Simulation time 37262780965 ps
CPU time 53.91 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:20:23 PM PDT 24
Peak memory 183180 kb
Host smart-0f2a159d-2ba9-4ed2-90e0-91d1f4d3bc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991876400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.991876400
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2089278433
Short name T299
Test name
Test status
Simulation time 371812234118 ps
CPU time 162.25 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:22:13 PM PDT 24
Peak memory 183172 kb
Host smart-255a4412-9cb0-44fa-be1f-8b066c5ee0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089278433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2089278433
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1661146915
Short name T351
Test name
Test status
Simulation time 778753907 ps
CPU time 4.86 seconds
Started Jun 28 07:19:04 PM PDT 24
Finished Jun 28 07:19:32 PM PDT 24
Peak memory 191228 kb
Host smart-96430473-73b4-4f80-b9a6-4d72b2da5b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661146915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1661146915
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2493606391
Short name T18
Test name
Test status
Simulation time 57633635 ps
CPU time 0.83 seconds
Started Jun 28 07:19:02 PM PDT 24
Finished Jun 28 07:19:26 PM PDT 24
Peak memory 213424 kb
Host smart-7c7de54c-83a8-4cc0-9911-dbcb51a3cc74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493606391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2493606391
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2848944357
Short name T222
Test name
Test status
Simulation time 378327518619 ps
CPU time 580.81 seconds
Started Jun 28 07:19:02 PM PDT 24
Finished Jun 28 07:29:06 PM PDT 24
Peak memory 191336 kb
Host smart-2a26be65-460c-45e9-a2ec-5d0f42563f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848944357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2848944357
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.4222689108
Short name T16
Test name
Test status
Simulation time 140186650598 ps
CPU time 398.09 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:26:08 PM PDT 24
Peak memory 206068 kb
Host smart-2ab8ba26-60fe-40ed-9401-e0869c491327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222689108 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.4222689108
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2846794566
Short name T411
Test name
Test status
Simulation time 144227115412 ps
CPU time 178.23 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:22:31 PM PDT 24
Peak memory 183168 kb
Host smart-364b7dc0-d2a9-40a4-8ffb-433ad581608d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846794566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2846794566
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.655962182
Short name T260
Test name
Test status
Simulation time 488907782882 ps
CPU time 682.96 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:30:53 PM PDT 24
Peak memory 191368 kb
Host smart-e8b9dd17-26ff-4a97-b0a3-d6281494cfa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655962182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.655962182
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3788143075
Short name T362
Test name
Test status
Simulation time 1079085442 ps
CPU time 1.41 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:19:36 PM PDT 24
Peak memory 183120 kb
Host smart-16737a00-29f4-4265-b6d4-bcb963cfaf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788143075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3788143075
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3277292950
Short name T424
Test name
Test status
Simulation time 78931906944 ps
CPU time 51.58 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:20:26 PM PDT 24
Peak memory 183108 kb
Host smart-dc308920-ea48-48db-afa7-fc2ee8d9d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277292950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3277292950
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3097444253
Short name T318
Test name
Test status
Simulation time 8573226087 ps
CPU time 18.13 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:19:53 PM PDT 24
Peak memory 194680 kb
Host smart-7ce6e797-4d38-4050-886b-14fde67e51ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097444253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3097444253
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.635095084
Short name T246
Test name
Test status
Simulation time 218761278020 ps
CPU time 349.91 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:25:23 PM PDT 24
Peak memory 183168 kb
Host smart-52cf8cea-41c5-455c-a96d-b430a1db74d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635095084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.635095084
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3827562477
Short name T377
Test name
Test status
Simulation time 49365986993 ps
CPU time 61.25 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:20:36 PM PDT 24
Peak memory 182956 kb
Host smart-2245c9df-a5b6-4ec8-bf7c-cf92206df6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827562477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3827562477
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.308356110
Short name T216
Test name
Test status
Simulation time 611607785959 ps
CPU time 368.65 seconds
Started Jun 28 07:19:12 PM PDT 24
Finished Jun 28 07:25:45 PM PDT 24
Peak memory 191296 kb
Host smart-54749293-e421-4653-a56b-5e456923e328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308356110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.308356110
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2833566329
Short name T396
Test name
Test status
Simulation time 17028692 ps
CPU time 0.54 seconds
Started Jun 28 07:19:10 PM PDT 24
Finished Jun 28 07:19:35 PM PDT 24
Peak memory 182944 kb
Host smart-b67fce63-5dcb-4990-b9f9-47c815afcd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833566329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2833566329
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4174820198
Short name T356
Test name
Test status
Simulation time 103702696258 ps
CPU time 116.4 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:21:31 PM PDT 24
Peak memory 194752 kb
Host smart-48286c93-08a7-4024-b33f-769dd7f8bec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174820198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4174820198
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2744716212
Short name T120
Test name
Test status
Simulation time 2638766553328 ps
CPU time 736.27 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:31:51 PM PDT 24
Peak memory 183160 kb
Host smart-48980acd-2656-4c0d-929e-4e185d15d6c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744716212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2744716212
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1464973521
Short name T375
Test name
Test status
Simulation time 117168279476 ps
CPU time 141.96 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:21:57 PM PDT 24
Peak memory 183180 kb
Host smart-47bb9f8b-0040-467e-9c9f-a20fb4269392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464973521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1464973521
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4253956671
Short name T337
Test name
Test status
Simulation time 35365320081 ps
CPU time 57.34 seconds
Started Jun 28 07:19:01 PM PDT 24
Finished Jun 28 07:20:21 PM PDT 24
Peak memory 191356 kb
Host smart-246480de-da40-4bfe-bb05-0cae15b0325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253956671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4253956671
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3546315390
Short name T147
Test name
Test status
Simulation time 28793131675 ps
CPU time 27.12 seconds
Started Jun 28 07:19:28 PM PDT 24
Finished Jun 28 07:20:12 PM PDT 24
Peak memory 183156 kb
Host smart-9e593d15-ed72-43c9-8cb9-45e21d2a1ae7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546315390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3546315390
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1571402321
Short name T380
Test name
Test status
Simulation time 314258072884 ps
CPU time 116.38 seconds
Started Jun 28 07:19:23 PM PDT 24
Finished Jun 28 07:21:38 PM PDT 24
Peak memory 183180 kb
Host smart-11f2f197-7484-4717-8909-d076f86e63fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571402321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1571402321
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.707258467
Short name T221
Test name
Test status
Simulation time 967262074331 ps
CPU time 1602.38 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:46:17 PM PDT 24
Peak memory 191364 kb
Host smart-078d4598-7803-4ca9-ba20-f3c863df613f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707258467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.707258467
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1602973142
Short name T251
Test name
Test status
Simulation time 77267119757 ps
CPU time 80.52 seconds
Started Jun 28 07:19:29 PM PDT 24
Finished Jun 28 07:21:08 PM PDT 24
Peak memory 183188 kb
Host smart-f44a4f15-eef0-49bb-8486-c2a1d460ccc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602973142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1602973142
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.4177392249
Short name T296
Test name
Test status
Simulation time 218943255820 ps
CPU time 531.67 seconds
Started Jun 28 07:19:28 PM PDT 24
Finished Jun 28 07:28:37 PM PDT 24
Peak memory 194728 kb
Host smart-ada629cd-addc-487d-89b2-58cfb9f001f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177392249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.4177392249
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2239416084
Short name T437
Test name
Test status
Simulation time 211865275974 ps
CPU time 80.72 seconds
Started Jun 28 07:19:22 PM PDT 24
Finished Jun 28 07:21:03 PM PDT 24
Peak memory 183168 kb
Host smart-09d6aad5-c41a-436d-9c68-ee9003c95a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239416084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2239416084
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1864065152
Short name T210
Test name
Test status
Simulation time 74496031249 ps
CPU time 53.27 seconds
Started Jun 28 07:19:23 PM PDT 24
Finished Jun 28 07:20:35 PM PDT 24
Peak memory 191368 kb
Host smart-695667e3-3a31-4ee9-ae49-d56df22e4eae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864065152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1864065152
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1221703578
Short name T22
Test name
Test status
Simulation time 8927409055 ps
CPU time 136.13 seconds
Started Jun 28 07:19:26 PM PDT 24
Finished Jun 28 07:22:00 PM PDT 24
Peak memory 183264 kb
Host smart-91116b23-02b4-4b7f-bcd1-3bed46abb49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221703578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1221703578
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1894534230
Short name T371
Test name
Test status
Simulation time 107694659789 ps
CPU time 44.12 seconds
Started Jun 28 07:19:30 PM PDT 24
Finished Jun 28 07:20:32 PM PDT 24
Peak memory 183180 kb
Host smart-cf6a32db-3028-49a9-b048-96db9029e577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894534230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1894534230
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1984676279
Short name T59
Test name
Test status
Simulation time 1896769069 ps
CPU time 1.15 seconds
Started Jun 28 07:19:27 PM PDT 24
Finished Jun 28 07:19:46 PM PDT 24
Peak memory 193552 kb
Host smart-07ceef54-686f-466a-aeaf-92fd1478e262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984676279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1984676279
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1931097890
Short name T61
Test name
Test status
Simulation time 646144271056 ps
CPU time 494.05 seconds
Started Jun 28 07:19:26 PM PDT 24
Finished Jun 28 07:27:58 PM PDT 24
Peak memory 194752 kb
Host smart-6b9d708a-8732-495b-9f7c-204315d39cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931097890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1931097890
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1545258596
Short name T177
Test name
Test status
Simulation time 125656339172 ps
CPU time 65.84 seconds
Started Jun 28 07:19:26 PM PDT 24
Finished Jun 28 07:20:50 PM PDT 24
Peak memory 183152 kb
Host smart-7166030b-2aea-4862-b127-ea85e88a6bab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545258596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1545258596
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3618382984
Short name T449
Test name
Test status
Simulation time 111077504206 ps
CPU time 26.17 seconds
Started Jun 28 07:19:26 PM PDT 24
Finished Jun 28 07:20:10 PM PDT 24
Peak memory 183176 kb
Host smart-428e5dbb-f7ea-42f5-addc-161e097acf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618382984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3618382984
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2661162647
Short name T149
Test name
Test status
Simulation time 22094555100 ps
CPU time 16.41 seconds
Started Jun 28 07:19:25 PM PDT 24
Finished Jun 28 07:20:00 PM PDT 24
Peak memory 191364 kb
Host smart-73e32b50-9b55-4e45-af88-554f2475b46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661162647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2661162647
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1726189756
Short name T376
Test name
Test status
Simulation time 559021219741 ps
CPU time 227.31 seconds
Started Jun 28 07:19:22 PM PDT 24
Finished Jun 28 07:23:29 PM PDT 24
Peak memory 183140 kb
Host smart-9de1dfd4-1359-41ca-bac9-32c69a511946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726189756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1726189756
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1534870070
Short name T232
Test name
Test status
Simulation time 106682758842 ps
CPU time 160.1 seconds
Started Jun 28 07:19:27 PM PDT 24
Finished Jun 28 07:22:24 PM PDT 24
Peak memory 191336 kb
Host smart-8986c6fd-a02e-4f38-8353-753178bd41c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534870070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1534870070
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.583491020
Short name T420
Test name
Test status
Simulation time 6282574137 ps
CPU time 11.16 seconds
Started Jun 28 07:19:21 PM PDT 24
Finished Jun 28 07:19:53 PM PDT 24
Peak memory 183172 kb
Host smart-29d4e80d-cf97-46b5-88a0-7cba2d0f22d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583491020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.583491020
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4030898666
Short name T388
Test name
Test status
Simulation time 167458999839 ps
CPU time 230.9 seconds
Started Jun 28 07:19:28 PM PDT 24
Finished Jun 28 07:23:38 PM PDT 24
Peak memory 183156 kb
Host smart-e2f763ac-a46b-484d-8518-d1eadc040e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030898666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4030898666
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1293258208
Short name T218
Test name
Test status
Simulation time 225398043954 ps
CPU time 408.39 seconds
Started Jun 28 07:19:28 PM PDT 24
Finished Jun 28 07:26:35 PM PDT 24
Peak memory 191328 kb
Host smart-25793ace-dbff-449b-bf71-a76803ce613b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293258208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1293258208
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.782951225
Short name T391
Test name
Test status
Simulation time 34951554877 ps
CPU time 61.86 seconds
Started Jun 28 07:19:21 PM PDT 24
Finished Jun 28 07:20:44 PM PDT 24
Peak memory 183176 kb
Host smart-ef1219c7-5aac-4879-8615-d833e2758352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782951225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.782951225
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1367327588
Short name T355
Test name
Test status
Simulation time 125050968478 ps
CPU time 101.81 seconds
Started Jun 28 07:19:23 PM PDT 24
Finished Jun 28 07:21:24 PM PDT 24
Peak memory 194816 kb
Host smart-28c183c1-19ee-468d-bf05-3287e1f26f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367327588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1367327588
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.282542093
Short name T49
Test name
Test status
Simulation time 414657815537 ps
CPU time 717.34 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:31:28 PM PDT 24
Peak memory 183124 kb
Host smart-ca8aebdb-20fc-4dc4-adcb-84363cfcff5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282542093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.282542093
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.194639435
Short name T423
Test name
Test status
Simulation time 525015196753 ps
CPU time 202.67 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:22:53 PM PDT 24
Peak memory 183180 kb
Host smart-ed8117e9-6417-41a1-84f5-f27bb14266aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194639435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.194639435
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.559769483
Short name T383
Test name
Test status
Simulation time 41503194127 ps
CPU time 31.02 seconds
Started Jun 28 07:19:01 PM PDT 24
Finished Jun 28 07:19:55 PM PDT 24
Peak memory 183152 kb
Host smart-e91ba777-4736-47fa-9e2a-2c077d9765cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559769483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.559769483
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1098296626
Short name T11
Test name
Test status
Simulation time 79173039 ps
CPU time 0.89 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:19:33 PM PDT 24
Peak memory 214168 kb
Host smart-f5082b77-6227-4b91-93f1-3e4100ef4118
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098296626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1098296626
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.983844239
Short name T48
Test name
Test status
Simulation time 410866663834 ps
CPU time 1011.26 seconds
Started Jun 28 07:19:04 PM PDT 24
Finished Jun 28 07:36:19 PM PDT 24
Peak memory 191304 kb
Host smart-e8d02106-0f0a-46a7-ae30-733ee3869e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983844239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.983844239
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4013001683
Short name T157
Test name
Test status
Simulation time 1419681380920 ps
CPU time 772.66 seconds
Started Jun 28 07:19:42 PM PDT 24
Finished Jun 28 07:32:52 PM PDT 24
Peak memory 183168 kb
Host smart-dd9c4d89-7ae7-44bf-af3c-63dd71b43994
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013001683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.4013001683
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3275158352
Short name T366
Test name
Test status
Simulation time 599155549693 ps
CPU time 175.81 seconds
Started Jun 28 07:19:38 PM PDT 24
Finished Jun 28 07:22:51 PM PDT 24
Peak memory 183176 kb
Host smart-6d50e97e-dab8-446b-a37a-7fe44d206081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275158352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3275158352
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.872043126
Short name T291
Test name
Test status
Simulation time 123639771749 ps
CPU time 1662.67 seconds
Started Jun 28 07:19:21 PM PDT 24
Finished Jun 28 07:47:25 PM PDT 24
Peak memory 191364 kb
Host smart-239135c6-a63c-45ad-890b-d74067e30487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872043126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.872043126
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1670638670
Short name T199
Test name
Test status
Simulation time 275909943174 ps
CPU time 101.2 seconds
Started Jun 28 07:19:37 PM PDT 24
Finished Jun 28 07:21:34 PM PDT 24
Peak memory 191384 kb
Host smart-a6386bf0-6af9-4147-8594-973a64783829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670638670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1670638670
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1163848298
Short name T276
Test name
Test status
Simulation time 2120818917673 ps
CPU time 1198.13 seconds
Started Jun 28 07:19:46 PM PDT 24
Finished Jun 28 07:40:03 PM PDT 24
Peak memory 191344 kb
Host smart-8a154aa9-af46-4588-9aee-37c77138ae00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163848298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1163848298
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3050461929
Short name T186
Test name
Test status
Simulation time 101662599897 ps
CPU time 155.08 seconds
Started Jun 28 07:19:41 PM PDT 24
Finished Jun 28 07:22:33 PM PDT 24
Peak memory 183160 kb
Host smart-8dc19490-328c-4f2b-96ed-9a089dc16e64
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050461929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3050461929
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3996240683
Short name T432
Test name
Test status
Simulation time 35554537139 ps
CPU time 40.48 seconds
Started Jun 28 07:19:41 PM PDT 24
Finished Jun 28 07:20:38 PM PDT 24
Peak memory 183180 kb
Host smart-f766d77a-290f-4118-8477-28834d4576b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996240683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3996240683
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3717941455
Short name T294
Test name
Test status
Simulation time 1331634162621 ps
CPU time 618.68 seconds
Started Jun 28 07:19:38 PM PDT 24
Finished Jun 28 07:30:14 PM PDT 24
Peak memory 194724 kb
Host smart-de6fdb05-1bfd-4442-b27a-d924699869fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717941455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3717941455
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3101736058
Short name T378
Test name
Test status
Simulation time 321794034 ps
CPU time 1.94 seconds
Started Jun 28 07:19:41 PM PDT 24
Finished Jun 28 07:20:00 PM PDT 24
Peak memory 191316 kb
Host smart-449fa499-eedf-4ab1-b194-7b884aa02075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101736058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3101736058
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1063094669
Short name T407
Test name
Test status
Simulation time 116554393113 ps
CPU time 83.08 seconds
Started Jun 28 07:19:40 PM PDT 24
Finished Jun 28 07:21:21 PM PDT 24
Peak memory 183164 kb
Host smart-79000088-9620-46e0-97ca-0aaed7820841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063094669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1063094669
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3939271596
Short name T453
Test name
Test status
Simulation time 5569460357 ps
CPU time 7.68 seconds
Started Jun 28 07:19:41 PM PDT 24
Finished Jun 28 07:20:06 PM PDT 24
Peak memory 183092 kb
Host smart-52a7e4f2-5733-434c-85d0-689d9f503605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939271596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3939271596
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1227132936
Short name T249
Test name
Test status
Simulation time 165507722918 ps
CPU time 185.41 seconds
Started Jun 28 07:19:46 PM PDT 24
Finished Jun 28 07:23:09 PM PDT 24
Peak memory 191348 kb
Host smart-c2b6285d-b196-4c20-b413-8adb835631b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227132936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1227132936
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2148850682
Short name T331
Test name
Test status
Simulation time 41122751109 ps
CPU time 941.52 seconds
Started Jun 28 07:19:40 PM PDT 24
Finished Jun 28 07:35:39 PM PDT 24
Peak memory 183188 kb
Host smart-cb7712ed-3cf3-411d-be01-839794593d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148850682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2148850682
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3477535942
Short name T231
Test name
Test status
Simulation time 1371826054585 ps
CPU time 776.72 seconds
Started Jun 28 07:19:34 PM PDT 24
Finished Jun 28 07:32:45 PM PDT 24
Peak memory 183152 kb
Host smart-bbcf128a-220f-4739-91f8-318def665b2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477535942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3477535942
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.155806149
Short name T427
Test name
Test status
Simulation time 106762993601 ps
CPU time 137.09 seconds
Started Jun 28 07:19:37 PM PDT 24
Finished Jun 28 07:22:09 PM PDT 24
Peak memory 183176 kb
Host smart-ef22fc65-ff22-4a2f-ad84-9e71488ebd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155806149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.155806149
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3649834001
Short name T122
Test name
Test status
Simulation time 338954443059 ps
CPU time 618.68 seconds
Started Jun 28 07:19:46 PM PDT 24
Finished Jun 28 07:30:23 PM PDT 24
Peak memory 191348 kb
Host smart-b9c1108e-c248-47ce-93ea-bed45a68e205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649834001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3649834001
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3059281297
Short name T154
Test name
Test status
Simulation time 105457434836 ps
CPU time 109.15 seconds
Started Jun 28 07:19:42 PM PDT 24
Finished Jun 28 07:21:48 PM PDT 24
Peak memory 183196 kb
Host smart-71442618-9465-4eb9-8119-14208e9295e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059281297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3059281297
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2822020454
Short name T413
Test name
Test status
Simulation time 100196514 ps
CPU time 0.56 seconds
Started Jun 28 07:19:41 PM PDT 24
Finished Jun 28 07:19:59 PM PDT 24
Peak memory 183012 kb
Host smart-0e9d9d36-f5ed-421c-854a-daf23d5046dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822020454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2822020454
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1616346379
Short name T402
Test name
Test status
Simulation time 275920049050 ps
CPU time 116.9 seconds
Started Jun 28 07:19:41 PM PDT 24
Finished Jun 28 07:21:54 PM PDT 24
Peak memory 183156 kb
Host smart-c4f76c51-4582-4f91-8efd-3d0a74351453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616346379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1616346379
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2874848784
Short name T127
Test name
Test status
Simulation time 347762981868 ps
CPU time 535.94 seconds
Started Jun 28 07:19:34 PM PDT 24
Finished Jun 28 07:28:45 PM PDT 24
Peak memory 191296 kb
Host smart-ed83d896-d451-4f09-ad6c-10ff3ae42814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874848784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2874848784
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2985959524
Short name T297
Test name
Test status
Simulation time 49188067562 ps
CPU time 336.55 seconds
Started Jun 28 07:19:40 PM PDT 24
Finished Jun 28 07:25:34 PM PDT 24
Peak memory 183188 kb
Host smart-c2d33f40-843f-4241-86c1-d1a28c9a265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985959524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2985959524
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.4197906631
Short name T26
Test name
Test status
Simulation time 183618497032 ps
CPU time 50.82 seconds
Started Jun 28 07:19:43 PM PDT 24
Finished Jun 28 07:20:52 PM PDT 24
Peak memory 183136 kb
Host smart-e5ac3c2d-34db-429f-818e-3ccca88f68ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197906631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.4197906631
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1703880775
Short name T28
Test name
Test status
Simulation time 6925073496 ps
CPU time 10.43 seconds
Started Jun 28 07:19:36 PM PDT 24
Finished Jun 28 07:20:02 PM PDT 24
Peak memory 183084 kb
Host smart-83776f53-fb46-41d5-b0c5-bad50250551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703880775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1703880775
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2050814038
Short name T179
Test name
Test status
Simulation time 39314557178 ps
CPU time 27.07 seconds
Started Jun 28 07:19:42 PM PDT 24
Finished Jun 28 07:20:26 PM PDT 24
Peak memory 183168 kb
Host smart-9c252188-64a0-4ca9-aef0-4abb4c78d2c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050814038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2050814038
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2885993957
Short name T201
Test name
Test status
Simulation time 103260944809 ps
CPU time 107.28 seconds
Started Jun 28 07:19:41 PM PDT 24
Finished Jun 28 07:21:45 PM PDT 24
Peak memory 183180 kb
Host smart-3b1a00d6-9840-4281-b8b4-86ba8c8d4474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885993957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2885993957
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1097045199
Short name T267
Test name
Test status
Simulation time 2678308574323 ps
CPU time 1494.43 seconds
Started Jun 28 07:19:40 PM PDT 24
Finished Jun 28 07:44:52 PM PDT 24
Peak memory 191364 kb
Host smart-bb816aae-bb0d-4c8a-b9fd-9e19259b4a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097045199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1097045199
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2516702005
Short name T410
Test name
Test status
Simulation time 39546970823 ps
CPU time 56.58 seconds
Started Jun 28 07:19:41 PM PDT 24
Finished Jun 28 07:20:55 PM PDT 24
Peak memory 183164 kb
Host smart-0d84395a-5550-4244-b93e-cd74d550e5f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516702005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2516702005
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.516060468
Short name T365
Test name
Test status
Simulation time 46291833457 ps
CPU time 61.06 seconds
Started Jun 28 07:19:40 PM PDT 24
Finished Jun 28 07:20:58 PM PDT 24
Peak memory 183128 kb
Host smart-77fd3db9-7788-4408-9066-392351e4d6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516060468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.516060468
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1411854050
Short name T439
Test name
Test status
Simulation time 882563893 ps
CPU time 8.93 seconds
Started Jun 28 07:19:40 PM PDT 24
Finished Jun 28 07:20:06 PM PDT 24
Peak memory 183044 kb
Host smart-b4c3d69a-be27-4664-a758-e7b8456f572d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411854050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1411854050
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2896049204
Short name T408
Test name
Test status
Simulation time 419110600 ps
CPU time 0.77 seconds
Started Jun 28 07:19:42 PM PDT 24
Finished Jun 28 07:20:01 PM PDT 24
Peak memory 191532 kb
Host smart-9056316e-1b9c-42e8-8ac9-e40669cb13f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896049204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2896049204
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.87957313
Short name T9
Test name
Test status
Simulation time 1731449005797 ps
CPU time 552.54 seconds
Started Jun 28 07:19:42 PM PDT 24
Finished Jun 28 07:29:12 PM PDT 24
Peak memory 195828 kb
Host smart-07756e77-41b7-4ea8-8419-cc5339b767f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87957313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.87957313
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3586587332
Short name T257
Test name
Test status
Simulation time 1511813783746 ps
CPU time 1372.91 seconds
Started Jun 28 07:19:47 PM PDT 24
Finished Jun 28 07:42:58 PM PDT 24
Peak memory 183140 kb
Host smart-946a0714-7458-4d58-b4b0-0f6ec62e5f88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586587332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3586587332
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1282748034
Short name T373
Test name
Test status
Simulation time 215780630651 ps
CPU time 92.45 seconds
Started Jun 28 07:19:40 PM PDT 24
Finished Jun 28 07:21:30 PM PDT 24
Peak memory 183120 kb
Host smart-caec72b3-df7e-4da3-99a7-173da6135124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282748034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1282748034
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1942738125
Short name T344
Test name
Test status
Simulation time 33505741160 ps
CPU time 57.37 seconds
Started Jun 28 07:19:42 PM PDT 24
Finished Jun 28 07:20:57 PM PDT 24
Peak memory 191376 kb
Host smart-567af89b-8a6a-4328-ab00-62e178c0b991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942738125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1942738125
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1651588280
Short name T241
Test name
Test status
Simulation time 339094897828 ps
CPU time 212.86 seconds
Started Jun 28 07:19:43 PM PDT 24
Finished Jun 28 07:23:34 PM PDT 24
Peak memory 191396 kb
Host smart-695e3072-0a80-493f-89e7-75ce0953b00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651588280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1651588280
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.481803997
Short name T205
Test name
Test status
Simulation time 177309842618 ps
CPU time 41.48 seconds
Started Jun 28 07:19:51 PM PDT 24
Finished Jun 28 07:20:51 PM PDT 24
Peak memory 183160 kb
Host smart-54c51699-d068-4097-adf9-7bb84d4b7b6d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481803997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.481803997
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random.2079184655
Short name T60
Test name
Test status
Simulation time 280631397493 ps
CPU time 166.66 seconds
Started Jun 28 07:19:51 PM PDT 24
Finished Jun 28 07:22:56 PM PDT 24
Peak memory 191364 kb
Host smart-473ab3e0-9ff2-4c10-a987-3f17088ee686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079184655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2079184655
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2240718913
Short name T311
Test name
Test status
Simulation time 69627926991 ps
CPU time 119.4 seconds
Started Jun 28 07:19:53 PM PDT 24
Finished Jun 28 07:22:10 PM PDT 24
Peak memory 191380 kb
Host smart-bf5dadea-b692-4333-914d-eb5754fa668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240718913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2240718913
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.35563703
Short name T417
Test name
Test status
Simulation time 154025806481 ps
CPU time 215.76 seconds
Started Jun 28 07:19:51 PM PDT 24
Finished Jun 28 07:23:45 PM PDT 24
Peak memory 191464 kb
Host smart-959ad942-674b-4181-92b6-2c11a9a523fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35563703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.35563703
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3224505393
Short name T428
Test name
Test status
Simulation time 10986803165 ps
CPU time 16.21 seconds
Started Jun 28 07:20:08 PM PDT 24
Finished Jun 28 07:20:42 PM PDT 24
Peak memory 183132 kb
Host smart-e5478a35-fb0f-4155-a3fb-a6ad1116ebce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224505393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3224505393
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3191724259
Short name T354
Test name
Test status
Simulation time 259961165791 ps
CPU time 90.09 seconds
Started Jun 28 07:20:09 PM PDT 24
Finished Jun 28 07:21:56 PM PDT 24
Peak memory 183172 kb
Host smart-81305741-53d8-4b0a-b8fb-6dbd31de7e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191724259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3191724259
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3428491699
Short name T138
Test name
Test status
Simulation time 320328031384 ps
CPU time 157.06 seconds
Started Jun 28 07:20:09 PM PDT 24
Finished Jun 28 07:23:03 PM PDT 24
Peak memory 191276 kb
Host smart-2851cf3d-a0f2-4a90-b81d-0b85a6f51e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428491699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3428491699
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3720028741
Short name T442
Test name
Test status
Simulation time 386873825604 ps
CPU time 510.51 seconds
Started Jun 28 07:20:09 PM PDT 24
Finished Jun 28 07:28:56 PM PDT 24
Peak memory 191360 kb
Host smart-f1bcef8f-e696-46ac-bf7a-7827375ef24d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720028741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3720028741
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3277834676
Short name T271
Test name
Test status
Simulation time 376593783014 ps
CPU time 343.74 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:25:15 PM PDT 24
Peak memory 183164 kb
Host smart-6aa9e5f4-45bf-4d30-86f4-7ea9fd1367b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277834676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3277834676
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2887000683
Short name T384
Test name
Test status
Simulation time 245647658920 ps
CPU time 177.42 seconds
Started Jun 28 07:19:04 PM PDT 24
Finished Jun 28 07:22:23 PM PDT 24
Peak memory 183124 kb
Host smart-c4c3ea6d-6a8d-4178-b0cc-8050f11b5732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887000683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2887000683
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3779750147
Short name T339
Test name
Test status
Simulation time 390400000178 ps
CPU time 259.38 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:23:48 PM PDT 24
Peak memory 191360 kb
Host smart-ae8e01ef-8a47-450f-bd40-af9e7273cd41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779750147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3779750147
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2454407449
Short name T20
Test name
Test status
Simulation time 568773062 ps
CPU time 0.73 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:19:31 PM PDT 24
Peak memory 214076 kb
Host smart-80b512e8-081c-4659-a585-39ccd76b600b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454407449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2454407449
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2299520203
Short name T421
Test name
Test status
Simulation time 284650300 ps
CPU time 0.55 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:19:30 PM PDT 24
Peak memory 182996 kb
Host smart-7c0eca67-c686-4335-b8b4-94bb4f819e08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299520203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2299520203
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1380018518
Short name T38
Test name
Test status
Simulation time 190671575549 ps
CPU time 376.53 seconds
Started Jun 28 07:19:03 PM PDT 24
Finished Jun 28 07:25:42 PM PDT 24
Peak memory 206072 kb
Host smart-7b3db69a-308f-4a58-949b-8ae2b8ca44d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380018518 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1380018518
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.464673916
Short name T212
Test name
Test status
Simulation time 139394792322 ps
CPU time 125.55 seconds
Started Jun 28 07:20:08 PM PDT 24
Finished Jun 28 07:22:31 PM PDT 24
Peak memory 183168 kb
Host smart-a899fe9a-a5cb-4b4c-9955-565523a6a5c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464673916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.464673916
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1684338812
Short name T435
Test name
Test status
Simulation time 200858335226 ps
CPU time 163.2 seconds
Started Jun 28 07:20:07 PM PDT 24
Finished Jun 28 07:23:09 PM PDT 24
Peak memory 183172 kb
Host smart-e8a97bb0-b541-4d3e-b090-a19692ab563d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684338812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1684338812
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3575978422
Short name T359
Test name
Test status
Simulation time 215392563 ps
CPU time 0.9 seconds
Started Jun 28 07:20:06 PM PDT 24
Finished Jun 28 07:20:25 PM PDT 24
Peak memory 191692 kb
Host smart-667e2b5f-448f-4df4-80b4-0657fbc553be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575978422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3575978422
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1644829564
Short name T352
Test name
Test status
Simulation time 36003485938 ps
CPU time 53.54 seconds
Started Jun 28 07:20:26 PM PDT 24
Finished Jun 28 07:21:33 PM PDT 24
Peak memory 183164 kb
Host smart-39ddaf13-4d03-4832-bfe8-661dd3130ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644829564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1644829564
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.619628006
Short name T326
Test name
Test status
Simulation time 783663549405 ps
CPU time 805.91 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 07:34:05 PM PDT 24
Peak memory 183144 kb
Host smart-644bdac6-d860-461a-ab96-9725e210c32d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619628006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.619628006
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.170046479
Short name T379
Test name
Test status
Simulation time 441799059617 ps
CPU time 112.92 seconds
Started Jun 28 07:20:27 PM PDT 24
Finished Jun 28 07:22:34 PM PDT 24
Peak memory 183180 kb
Host smart-1697b640-c50b-4ff6-b108-d3df2dc52a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170046479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.170046479
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3994417833
Short name T310
Test name
Test status
Simulation time 159662414163 ps
CPU time 82.02 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 07:22:01 PM PDT 24
Peak memory 183080 kb
Host smart-06aa840a-29cb-4014-8a2d-f4d1cabd96e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994417833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3994417833
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3061956847
Short name T438
Test name
Test status
Simulation time 67946768980 ps
CPU time 52.45 seconds
Started Jun 28 07:20:25 PM PDT 24
Finished Jun 28 07:21:31 PM PDT 24
Peak memory 183152 kb
Host smart-5b92f44c-d266-4a8d-a5a1-01406fced253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061956847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3061956847
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3203876600
Short name T304
Test name
Test status
Simulation time 437525518735 ps
CPU time 675.11 seconds
Started Jun 28 07:20:27 PM PDT 24
Finished Jun 28 07:31:56 PM PDT 24
Peak memory 183188 kb
Host smart-275fe818-5152-4906-8ee8-f6fd5587a8de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203876600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3203876600
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3060264232
Short name T419
Test name
Test status
Simulation time 408969620406 ps
CPU time 293.45 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 07:25:32 PM PDT 24
Peak memory 183188 kb
Host smart-4178b1ec-74bf-477a-9742-41d264e72eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060264232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3060264232
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1932753069
Short name T171
Test name
Test status
Simulation time 722492822054 ps
CPU time 585.95 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 07:30:25 PM PDT 24
Peak memory 191360 kb
Host smart-699e47eb-2f09-4b25-9566-409253cdaffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932753069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1932753069
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3658985895
Short name T23
Test name
Test status
Simulation time 46467998304 ps
CPU time 170.92 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 07:23:30 PM PDT 24
Peak memory 183164 kb
Host smart-52cab683-d9c0-4dae-a3ae-9163f0a4827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658985895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3658985895
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2221522920
Short name T132
Test name
Test status
Simulation time 207658775391 ps
CPU time 338.27 seconds
Started Jun 28 07:20:23 PM PDT 24
Finished Jun 28 07:26:17 PM PDT 24
Peak memory 183156 kb
Host smart-0a47064e-e15d-4a7e-8977-8f8bac4475cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221522920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2221522920
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3158306718
Short name T353
Test name
Test status
Simulation time 8064344511 ps
CPU time 6.36 seconds
Started Jun 28 07:20:23 PM PDT 24
Finished Jun 28 07:20:44 PM PDT 24
Peak memory 183180 kb
Host smart-3371599b-ed2f-47d5-a7d3-9072fb3a9c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158306718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3158306718
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.4102769538
Short name T121
Test name
Test status
Simulation time 369668679128 ps
CPU time 259.73 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 07:24:58 PM PDT 24
Peak memory 191352 kb
Host smart-9a322dec-3c12-4dd2-9b32-3088785478c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102769538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4102769538
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3714076309
Short name T431
Test name
Test status
Simulation time 198879083 ps
CPU time 0.64 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 07:20:39 PM PDT 24
Peak memory 183036 kb
Host smart-4fdb4677-4e8d-4202-a3d7-c95d6d41d77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714076309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3714076309
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1646036619
Short name T37
Test name
Test status
Simulation time 146962999342 ps
CPU time 777.22 seconds
Started Jun 28 07:20:24 PM PDT 24
Finished Jun 28 07:33:36 PM PDT 24
Peak memory 201764 kb
Host smart-d1b2d5c1-8ea5-48ec-ae89-36c9f27f4f9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646036619 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1646036619
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1097972285
Short name T228
Test name
Test status
Simulation time 1559198716608 ps
CPU time 685.6 seconds
Started Jun 28 07:20:45 PM PDT 24
Finished Jun 28 07:32:19 PM PDT 24
Peak memory 183160 kb
Host smart-f826641a-8874-48a3-9960-95d816e333eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097972285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1097972285
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1514797011
Short name T404
Test name
Test status
Simulation time 285574113606 ps
CPU time 121.65 seconds
Started Jun 28 07:20:26 PM PDT 24
Finished Jun 28 07:22:41 PM PDT 24
Peak memory 183180 kb
Host smart-fca5f4da-2898-4382-bdb4-14943da03206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514797011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1514797011
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1159066668
Short name T389
Test name
Test status
Simulation time 9799337171 ps
CPU time 18.56 seconds
Started Jun 28 07:20:43 PM PDT 24
Finished Jun 28 07:21:10 PM PDT 24
Peak memory 191396 kb
Host smart-a616f771-c45a-4439-8dd0-96df4cbeea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159066668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1159066668
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.594051511
Short name T39
Test name
Test status
Simulation time 13665992633 ps
CPU time 108.79 seconds
Started Jun 28 07:20:45 PM PDT 24
Finished Jun 28 07:22:42 PM PDT 24
Peak memory 197888 kb
Host smart-380d2030-8620-4141-b32e-a38e8567dde5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594051511 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.594051511
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3314700427
Short name T381
Test name
Test status
Simulation time 17263347691 ps
CPU time 22.03 seconds
Started Jun 28 07:20:44 PM PDT 24
Finished Jun 28 07:21:14 PM PDT 24
Peak memory 183180 kb
Host smart-a956b74b-d18f-4e84-9ac3-7a1f4e2db71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314700427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3314700427
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3072194892
Short name T256
Test name
Test status
Simulation time 62633615924 ps
CPU time 98.85 seconds
Started Jun 28 07:20:44 PM PDT 24
Finished Jun 28 07:22:31 PM PDT 24
Peak memory 191360 kb
Host smart-6e0feb88-28bf-477d-b76b-7c9dc3660010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072194892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3072194892
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2561729353
Short name T387
Test name
Test status
Simulation time 176375499 ps
CPU time 2.02 seconds
Started Jun 28 07:20:42 PM PDT 24
Finished Jun 28 07:20:52 PM PDT 24
Peak memory 183124 kb
Host smart-828fd6a2-8539-4ee1-9f25-3f6f05e69fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561729353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2561729353
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1568618316
Short name T17
Test name
Test status
Simulation time 83850553319 ps
CPU time 338.93 seconds
Started Jun 28 07:20:43 PM PDT 24
Finished Jun 28 07:26:30 PM PDT 24
Peak memory 206068 kb
Host smart-be84d483-b2f3-43f6-abe1-63abcaeb147b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568618316 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1568618316
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2619517783
Short name T42
Test name
Test status
Simulation time 60678582413 ps
CPU time 32.89 seconds
Started Jun 28 07:20:42 PM PDT 24
Finished Jun 28 07:21:23 PM PDT 24
Peak memory 183160 kb
Host smart-20da2c71-a0d4-4328-b21e-597cf8cbf622
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619517783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2619517783
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3173959812
Short name T360
Test name
Test status
Simulation time 226880344143 ps
CPU time 159.46 seconds
Started Jun 28 07:20:42 PM PDT 24
Finished Jun 28 07:23:30 PM PDT 24
Peak memory 183148 kb
Host smart-6de9fc78-7884-47d1-9a96-ec9a5829ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173959812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3173959812
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2065968348
Short name T454
Test name
Test status
Simulation time 359967751124 ps
CPU time 85.93 seconds
Started Jun 28 07:20:44 PM PDT 24
Finished Jun 28 07:22:18 PM PDT 24
Peak memory 191360 kb
Host smart-e2152d9d-38cb-4767-a0d8-7a0a6a5c556b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065968348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2065968348
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3280213149
Short name T289
Test name
Test status
Simulation time 44571035942 ps
CPU time 71.13 seconds
Started Jun 28 07:20:45 PM PDT 24
Finished Jun 28 07:22:04 PM PDT 24
Peak memory 183184 kb
Host smart-e0e87751-80d9-4304-bef8-bcf680b2dc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280213149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3280213149
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1761531965
Short name T245
Test name
Test status
Simulation time 290955440466 ps
CPU time 131.11 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:23:24 PM PDT 24
Peak memory 183152 kb
Host smart-f35f12bb-4da2-4c70-86a1-2fe13e2840c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761531965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1761531965
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.537341243
Short name T416
Test name
Test status
Simulation time 270358492904 ps
CPU time 186.59 seconds
Started Jun 28 07:21:08 PM PDT 24
Finished Jun 28 07:24:17 PM PDT 24
Peak memory 183128 kb
Host smart-7b3e26b1-a34e-4dd2-9a18-0ca66fd9c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537341243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.537341243
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2297471112
Short name T73
Test name
Test status
Simulation time 365105163576 ps
CPU time 363.1 seconds
Started Jun 28 07:20:44 PM PDT 24
Finished Jun 28 07:26:55 PM PDT 24
Peak memory 191396 kb
Host smart-8d5d9d3b-5a95-4c14-9f6c-e463b3c27682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297471112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2297471112
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.645397169
Short name T444
Test name
Test status
Simulation time 959827636 ps
CPU time 1.02 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:21:14 PM PDT 24
Peak memory 183096 kb
Host smart-3ebc6676-6beb-4cf0-8a70-37c05de86508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645397169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.645397169
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4288018759
Short name T367
Test name
Test status
Simulation time 39585482877 ps
CPU time 59.16 seconds
Started Jun 28 07:21:10 PM PDT 24
Finished Jun 28 07:22:13 PM PDT 24
Peak memory 183172 kb
Host smart-b0e19224-2046-4bc3-a095-70d2979de2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288018759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4288018759
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3620921750
Short name T343
Test name
Test status
Simulation time 187011599802 ps
CPU time 48.3 seconds
Started Jun 28 07:21:08 PM PDT 24
Finished Jun 28 07:22:00 PM PDT 24
Peak memory 183156 kb
Host smart-0103eb76-d52c-4253-883f-05d0dbe5a119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620921750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3620921750
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.998586378
Short name T415
Test name
Test status
Simulation time 128156859215 ps
CPU time 87.76 seconds
Started Jun 28 07:21:10 PM PDT 24
Finished Jun 28 07:22:42 PM PDT 24
Peak memory 194620 kb
Host smart-05324e90-9881-471b-95f6-98720fb3b407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998586378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.998586378
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4079270784
Short name T335
Test name
Test status
Simulation time 5907206103 ps
CPU time 5.6 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:21:19 PM PDT 24
Peak memory 183160 kb
Host smart-c1b4bac6-5cb9-4c70-88a6-77a85ac006b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079270784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4079270784
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.388372528
Short name T385
Test name
Test status
Simulation time 180832760558 ps
CPU time 132.91 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:23:26 PM PDT 24
Peak memory 183176 kb
Host smart-f076aa40-c40d-48a4-aeaf-b8b4e234f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388372528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.388372528
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4200521402
Short name T130
Test name
Test status
Simulation time 45213616134 ps
CPU time 86.93 seconds
Started Jun 28 07:21:11 PM PDT 24
Finished Jun 28 07:22:42 PM PDT 24
Peak memory 191344 kb
Host smart-a95ea7fd-9705-476d-aa2b-3981c1c4561d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200521402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4200521402
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2234804883
Short name T361
Test name
Test status
Simulation time 82254842 ps
CPU time 0.75 seconds
Started Jun 28 07:21:08 PM PDT 24
Finished Jun 28 07:21:12 PM PDT 24
Peak memory 183012 kb
Host smart-ad01a46b-eb19-4ac5-bf00-15177007116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234804883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2234804883
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3960790246
Short name T145
Test name
Test status
Simulation time 388636130549 ps
CPU time 217.68 seconds
Started Jun 28 07:21:08 PM PDT 24
Finished Jun 28 07:24:50 PM PDT 24
Peak memory 191364 kb
Host smart-c192679b-38ee-41af-9401-e0ab1ad1c6ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960790246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3960790246
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3473248919
Short name T430
Test name
Test status
Simulation time 1085205134874 ps
CPU time 505.02 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:28:00 PM PDT 24
Peak memory 183156 kb
Host smart-b47d2b4e-0421-4897-9aa9-82fe77155df0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473248919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3473248919
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3277434799
Short name T405
Test name
Test status
Simulation time 81966514631 ps
CPU time 111.99 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:21:26 PM PDT 24
Peak memory 183176 kb
Host smart-6e8ed21e-b1fe-4549-8350-625e8961fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277434799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3277434799
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2726695193
Short name T195
Test name
Test status
Simulation time 414331743969 ps
CPU time 204.23 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:22:53 PM PDT 24
Peak memory 191368 kb
Host smart-5a8dca36-3446-4afc-b92a-8504c42c9a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726695193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2726695193
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.293541991
Short name T447
Test name
Test status
Simulation time 49996828952 ps
CPU time 116.03 seconds
Started Jun 28 07:19:03 PM PDT 24
Finished Jun 28 07:21:22 PM PDT 24
Peak memory 183176 kb
Host smart-8969bc38-d0f8-466f-aac8-e5681da06ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293541991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.293541991
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4146070929
Short name T309
Test name
Test status
Simulation time 1931568172707 ps
CPU time 1033.89 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:36:43 PM PDT 24
Peak memory 195444 kb
Host smart-2d6f9f80-d3a8-472f-ac77-8d86ff3d6d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146070929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4146070929
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1975609682
Short name T106
Test name
Test status
Simulation time 323422057197 ps
CPU time 251.47 seconds
Started Jun 28 07:21:08 PM PDT 24
Finished Jun 28 07:25:24 PM PDT 24
Peak memory 191356 kb
Host smart-fa8d4c68-c2ef-47bb-983b-17ae2f5918de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975609682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1975609682
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2525170335
Short name T401
Test name
Test status
Simulation time 23847344479 ps
CPU time 237.96 seconds
Started Jun 28 07:21:11 PM PDT 24
Finished Jun 28 07:25:13 PM PDT 24
Peak memory 183160 kb
Host smart-af00f9a9-315a-4881-a495-408c8c5b8d16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525170335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2525170335
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2594624928
Short name T448
Test name
Test status
Simulation time 1106742111554 ps
CPU time 1205.57 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:41:19 PM PDT 24
Peak memory 191368 kb
Host smart-0dc19818-5636-430c-91d3-5bce5fc50865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594624928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2594624928
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3201448302
Short name T254
Test name
Test status
Simulation time 176085036627 ps
CPU time 76 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:22:29 PM PDT 24
Peak memory 183136 kb
Host smart-bd4467e4-5fa5-4528-8345-5bb17ac0beee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201448302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3201448302
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1057596371
Short name T292
Test name
Test status
Simulation time 79949531428 ps
CPU time 64.98 seconds
Started Jun 28 07:21:09 PM PDT 24
Finished Jun 28 07:22:18 PM PDT 24
Peak memory 183300 kb
Host smart-0e50c7fe-c7b5-479c-b753-630a9864915a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057596371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1057596371
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.448883534
Short name T412
Test name
Test status
Simulation time 77882093527 ps
CPU time 294.02 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:26:27 PM PDT 24
Peak memory 191364 kb
Host smart-acce2e91-20e7-432a-9051-2ed6fb63a8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448883534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.448883534
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1482559591
Short name T280
Test name
Test status
Simulation time 48136997664 ps
CPU time 77.31 seconds
Started Jun 28 07:21:26 PM PDT 24
Finished Jun 28 07:22:48 PM PDT 24
Peak memory 191308 kb
Host smart-fe8ea587-68ec-4bb8-92d4-14c12d150767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482559591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1482559591
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2063255432
Short name T288
Test name
Test status
Simulation time 4697857241 ps
CPU time 14.38 seconds
Started Jun 28 07:21:28 PM PDT 24
Finished Jun 28 07:21:49 PM PDT 24
Peak memory 183160 kb
Host smart-51629f83-fdc7-4a75-8d5e-0ba94896d0c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063255432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2063255432
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3637192122
Short name T223
Test name
Test status
Simulation time 315301333323 ps
CPU time 146.98 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:21:58 PM PDT 24
Peak memory 183136 kb
Host smart-7ac8fd96-6887-40fa-8ce8-61f8d64c4cb2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637192122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3637192122
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.212333488
Short name T399
Test name
Test status
Simulation time 65958185684 ps
CPU time 53.14 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:20:23 PM PDT 24
Peak memory 183184 kb
Host smart-f728804c-bfce-4120-a839-841530961205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212333488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.212333488
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.179505504
Short name T133
Test name
Test status
Simulation time 576726826747 ps
CPU time 241.98 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:23:32 PM PDT 24
Peak memory 191364 kb
Host smart-50c048e6-4da2-41bb-9987-3088333d177a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179505504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.179505504
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.696801683
Short name T131
Test name
Test status
Simulation time 29905751629 ps
CPU time 55.33 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:20:23 PM PDT 24
Peak memory 191380 kb
Host smart-71f415c7-b398-4705-b756-6243d557a3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696801683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.696801683
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3809102080
Short name T160
Test name
Test status
Simulation time 298314937176 ps
CPU time 100.37 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:23:14 PM PDT 24
Peak memory 191328 kb
Host smart-e10d25f1-c185-4ef1-aed5-f3ee12195e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809102080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3809102080
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2578153079
Short name T143
Test name
Test status
Simulation time 505828905684 ps
CPU time 357.89 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:27:27 PM PDT 24
Peak memory 191312 kb
Host smart-ea7a7946-154d-414b-9583-ec7caa693c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578153079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2578153079
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.889628974
Short name T342
Test name
Test status
Simulation time 160339632803 ps
CPU time 96.9 seconds
Started Jun 28 07:21:26 PM PDT 24
Finished Jun 28 07:23:09 PM PDT 24
Peak memory 191200 kb
Host smart-d99faef9-3cf0-43b4-8814-bae72106a530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889628974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.889628974
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2294322020
Short name T349
Test name
Test status
Simulation time 167262487079 ps
CPU time 88.75 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:23:01 PM PDT 24
Peak memory 191320 kb
Host smart-d007f215-0f7b-4627-b164-1424b2844471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294322020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2294322020
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.727628050
Short name T320
Test name
Test status
Simulation time 145556777907 ps
CPU time 58.1 seconds
Started Jun 28 07:21:30 PM PDT 24
Finished Jun 28 07:22:33 PM PDT 24
Peak memory 183092 kb
Host smart-481df864-2441-44c4-8b9f-03d53343dbb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727628050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.727628050
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2255706731
Short name T196
Test name
Test status
Simulation time 57302704763 ps
CPU time 90 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:22:59 PM PDT 24
Peak memory 191364 kb
Host smart-9bc89ce4-ce34-49f3-9263-08766f9291a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255706731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2255706731
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1896988912
Short name T240
Test name
Test status
Simulation time 51191046361 ps
CPU time 340.62 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:27:08 PM PDT 24
Peak memory 183168 kb
Host smart-0af49d44-f7fd-4e25-86ff-038996a1f9d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896988912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1896988912
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.45642656
Short name T113
Test name
Test status
Simulation time 85055736511 ps
CPU time 310.31 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:26:39 PM PDT 24
Peak memory 191356 kb
Host smart-67df6234-961b-4348-bc20-f2f627ecf463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45642656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.45642656
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3375713055
Short name T58
Test name
Test status
Simulation time 30799264783 ps
CPU time 32.49 seconds
Started Jun 28 07:21:25 PM PDT 24
Finished Jun 28 07:22:03 PM PDT 24
Peak memory 183168 kb
Host smart-26c25154-7227-4779-b5ed-364990c72279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375713055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3375713055
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3710618452
Short name T185
Test name
Test status
Simulation time 126020030725 ps
CPU time 184.22 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:22:35 PM PDT 24
Peak memory 183176 kb
Host smart-80130fbe-db32-4725-84ef-7b8022b7643e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710618452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3710618452
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1127608524
Short name T364
Test name
Test status
Simulation time 401185101875 ps
CPU time 154.86 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:22:07 PM PDT 24
Peak memory 183196 kb
Host smart-f6031607-6179-4f54-9598-9b9367a53836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127608524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1127608524
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3476553939
Short name T41
Test name
Test status
Simulation time 1117503519558 ps
CPU time 338.66 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:25:12 PM PDT 24
Peak memory 191340 kb
Host smart-a791ae09-c3a5-492e-a291-d09412fb3404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476553939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3476553939
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.995920807
Short name T363
Test name
Test status
Simulation time 1552101227 ps
CPU time 0.92 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:19:30 PM PDT 24
Peak memory 183024 kb
Host smart-d69d1e83-4e81-4fad-8f9d-ea5b02551634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995920807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.995920807
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2125991279
Short name T237
Test name
Test status
Simulation time 45933390595 ps
CPU time 37.82 seconds
Started Jun 28 07:21:26 PM PDT 24
Finished Jun 28 07:22:09 PM PDT 24
Peak memory 191360 kb
Host smart-595e2eff-cb2e-4025-927a-7d1562073414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125991279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2125991279
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1550896973
Short name T111
Test name
Test status
Simulation time 777454953352 ps
CPU time 393.96 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:28:07 PM PDT 24
Peak memory 191368 kb
Host smart-3f5df832-eb71-4794-839d-5640a1844247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550896973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1550896973
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1634750968
Short name T167
Test name
Test status
Simulation time 173828746397 ps
CPU time 297.83 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:26:31 PM PDT 24
Peak memory 191212 kb
Host smart-7961cb4b-51f4-4915-a25a-1c7ae7695c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634750968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1634750968
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2536809990
Short name T261
Test name
Test status
Simulation time 1705566746524 ps
CPU time 3353 seconds
Started Jun 28 07:21:25 PM PDT 24
Finished Jun 28 08:17:24 PM PDT 24
Peak memory 191360 kb
Host smart-4a03aba0-0ff4-4f47-a44c-c56965252927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536809990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2536809990
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3368767230
Short name T5
Test name
Test status
Simulation time 703584092886 ps
CPU time 518.65 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:30:08 PM PDT 24
Peak memory 191368 kb
Host smart-a842d8a5-3c94-4d96-b693-c4b81a2c237b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368767230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3368767230
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3716452538
Short name T426
Test name
Test status
Simulation time 32286733129 ps
CPU time 53.25 seconds
Started Jun 28 07:21:25 PM PDT 24
Finished Jun 28 07:22:24 PM PDT 24
Peak memory 194432 kb
Host smart-733f1014-e0d5-44f6-a7a1-080342a91e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716452538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3716452538
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3499848682
Short name T300
Test name
Test status
Simulation time 1822338849794 ps
CPU time 933.51 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:35:03 PM PDT 24
Peak memory 183156 kb
Host smart-277a17f8-a099-4e6c-b985-1d6d4c4f0df5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499848682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3499848682
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3538918709
Short name T357
Test name
Test status
Simulation time 114122335910 ps
CPU time 163.71 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:22:15 PM PDT 24
Peak memory 183196 kb
Host smart-dd01a9ef-9e2d-48c7-91bf-debd164f429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538918709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3538918709
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1423304713
Short name T159
Test name
Test status
Simulation time 206059657203 ps
CPU time 183.56 seconds
Started Jun 28 07:19:09 PM PDT 24
Finished Jun 28 07:22:38 PM PDT 24
Peak memory 193176 kb
Host smart-99696870-222e-47e1-8e3c-9a3cef3f2d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423304713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1423304713
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2538526067
Short name T446
Test name
Test status
Simulation time 9246291942 ps
CPU time 110.49 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:21:24 PM PDT 24
Peak memory 191356 kb
Host smart-e26c6d23-9e7d-4c4b-9b5f-0fee2099b0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538526067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2538526067
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.600573825
Short name T72
Test name
Test status
Simulation time 582620517439 ps
CPU time 245.8 seconds
Started Jun 28 07:19:08 PM PDT 24
Finished Jun 28 07:23:38 PM PDT 24
Peak memory 183136 kb
Host smart-ac4a0c8a-6fa8-402e-99a1-a0506b038ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600573825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.600573825
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.630361749
Short name T75
Test name
Test status
Simulation time 1096606933576 ps
CPU time 732.82 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:33:40 PM PDT 24
Peak memory 191364 kb
Host smart-a6f5e93f-5fd7-41be-9872-9f48d72df2c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630361749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.630361749
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3259858326
Short name T321
Test name
Test status
Simulation time 47402626309 ps
CPU time 252.27 seconds
Started Jun 28 07:21:28 PM PDT 24
Finished Jun 28 07:25:47 PM PDT 24
Peak memory 191368 kb
Host smart-3a4334dd-cb2d-417f-8ca6-ee5c0d51e180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259858326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3259858326
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1874491680
Short name T441
Test name
Test status
Simulation time 47187790338 ps
CPU time 81.71 seconds
Started Jun 28 07:21:25 PM PDT 24
Finished Jun 28 07:22:52 PM PDT 24
Peak memory 191364 kb
Host smart-8a3932bb-bba6-456a-8acb-1af199ac30f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874491680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1874491680
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3925436804
Short name T347
Test name
Test status
Simulation time 2407316021594 ps
CPU time 738.1 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:33:51 PM PDT 24
Peak memory 191212 kb
Host smart-ffc841a1-d7b3-4f6a-b313-c976a629658d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925436804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3925436804
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3455273652
Short name T64
Test name
Test status
Simulation time 768211739059 ps
CPU time 390.39 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:27:58 PM PDT 24
Peak memory 191396 kb
Host smart-c4c89204-97ec-4c6f-84e4-60927cc3f1f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455273652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3455273652
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3228952118
Short name T243
Test name
Test status
Simulation time 67362075736 ps
CPU time 131.31 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:23:41 PM PDT 24
Peak memory 191224 kb
Host smart-c056d32e-74dd-479e-9fb5-9b41f0551971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228952118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3228952118
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.694075757
Short name T436
Test name
Test status
Simulation time 49318346610 ps
CPU time 72.73 seconds
Started Jun 28 07:21:31 PM PDT 24
Finished Jun 28 07:22:48 PM PDT 24
Peak memory 191292 kb
Host smart-0a96253a-65fb-4745-b9a4-4fda939a6730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694075757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.694075757
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2597106006
Short name T150
Test name
Test status
Simulation time 48705471975 ps
CPU time 87.16 seconds
Started Jun 28 07:19:07 PM PDT 24
Finished Jun 28 07:20:58 PM PDT 24
Peak memory 183168 kb
Host smart-dcfaea8b-a28b-4fe7-9be6-b1df6bef8002
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597106006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2597106006
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.416164378
Short name T358
Test name
Test status
Simulation time 84075992505 ps
CPU time 132.12 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:21:43 PM PDT 24
Peak memory 183172 kb
Host smart-652350b5-bedd-4f01-8ee1-a748e7ff4ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416164378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.416164378
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2149907602
Short name T197
Test name
Test status
Simulation time 257543599228 ps
CPU time 125.8 seconds
Started Jun 28 07:19:06 PM PDT 24
Finished Jun 28 07:21:36 PM PDT 24
Peak memory 191364 kb
Host smart-bb713dc1-aba8-47c2-93a5-0b0cc62cd78a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149907602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2149907602
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2244218055
Short name T268
Test name
Test status
Simulation time 43701843454 ps
CPU time 36.66 seconds
Started Jun 28 07:19:05 PM PDT 24
Finished Jun 28 07:20:06 PM PDT 24
Peak memory 183180 kb
Host smart-08711122-20d0-4abe-8cb7-1bde56be6213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244218055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2244218055
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1106865730
Short name T369
Test name
Test status
Simulation time 580037003950 ps
CPU time 273.19 seconds
Started Jun 28 07:18:47 PM PDT 24
Finished Jun 28 07:23:21 PM PDT 24
Peak memory 191352 kb
Host smart-faab1657-6e82-457a-8131-dd01d1d28573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106865730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1106865730
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.3744104133
Short name T340
Test name
Test status
Simulation time 82633589010 ps
CPU time 486.02 seconds
Started Jun 28 07:21:25 PM PDT 24
Finished Jun 28 07:29:36 PM PDT 24
Peak memory 191360 kb
Host smart-830a6e7b-ce2d-45bd-a2fe-e75ea1736669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744104133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3744104133
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3490355065
Short name T313
Test name
Test status
Simulation time 103592291932 ps
CPU time 36.39 seconds
Started Jun 28 07:21:26 PM PDT 24
Finished Jun 28 07:22:07 PM PDT 24
Peak memory 183168 kb
Host smart-923fa081-ce38-4a69-9b21-46a83940ddda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490355065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3490355065
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.165629735
Short name T44
Test name
Test status
Simulation time 442458565557 ps
CPU time 628.89 seconds
Started Jun 28 07:21:28 PM PDT 24
Finished Jun 28 07:32:03 PM PDT 24
Peak memory 191356 kb
Host smart-67410702-5eeb-4c8b-9f5e-68f34cd1e91b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165629735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.165629735
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.643523111
Short name T117
Test name
Test status
Simulation time 597380528353 ps
CPU time 1232.9 seconds
Started Jun 28 07:21:27 PM PDT 24
Finished Jun 28 07:42:06 PM PDT 24
Peak memory 191356 kb
Host smart-3eb04a1b-c294-49c7-a06b-eb98895822a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643523111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.643523111
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3247778590
Short name T233
Test name
Test status
Simulation time 337656301105 ps
CPU time 830.03 seconds
Started Jun 28 07:21:24 PM PDT 24
Finished Jun 28 07:35:20 PM PDT 24
Peak memory 191328 kb
Host smart-a7f60257-66c8-4fa2-83f0-16db25f1e953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247778590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3247778590
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2972379183
Short name T451
Test name
Test status
Simulation time 715046283132 ps
CPU time 493.28 seconds
Started Jun 28 07:21:26 PM PDT 24
Finished Jun 28 07:29:45 PM PDT 24
Peak memory 194408 kb
Host smart-3b6ecf16-0e73-4215-ad13-8ad5bfd092c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972379183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2972379183
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.995728926
Short name T315
Test name
Test status
Simulation time 13065976769 ps
CPU time 19.24 seconds
Started Jun 28 07:21:41 PM PDT 24
Finished Jun 28 07:22:05 PM PDT 24
Peak memory 183168 kb
Host smart-215167ac-95cf-4d71-8a0c-f22632359ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995728926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.995728926
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3729071142
Short name T440
Test name
Test status
Simulation time 99588062963 ps
CPU time 321.7 seconds
Started Jun 28 07:21:40 PM PDT 24
Finished Jun 28 07:27:06 PM PDT 24
Peak memory 191344 kb
Host smart-c33e7dc6-bd0d-4a0a-99a3-5f20837c1265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729071142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3729071142
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2693990256
Short name T194
Test name
Test status
Simulation time 1189171833179 ps
CPU time 476.84 seconds
Started Jun 28 07:21:42 PM PDT 24
Finished Jun 28 07:29:43 PM PDT 24
Peak memory 191368 kb
Host smart-4d0a9449-a20d-4a0e-a538-00fc32a018dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693990256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2693990256
Directory /workspace/99.rv_timer_random/latest
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