| | | | | | | |
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
rv_timer |
95.83 |
100.00 |
83.33 |
100.00 |
|
|
100.00 |
tlul_adapter_reg |
98.91 |
100.00 |
95.65 |
|
|
100.00 |
100.00 |
rv_timer_reg_top |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
rv_timer_csr_assert_fpv |
100.00 |
|
|
|
|
|
100.00 |
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
prim_subreg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
prim_subreg ( parameter DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=12,SwAccess=0,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=32,SwAccess=0,RESVAL,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg ( parameter DW=8,SwAccess=0,RESVAL=1,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
prim_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_subreg_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=12,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
timer_core |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|