Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65032067	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	66077627	1		T1	89766		T2	488233		T3	88593

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	130190205	1		T1	179423		T2	977731		T3	32177
values[0x0]	436594	1		T1	16		T2	52		T3	31954
values[0x1]	482895	1		T1	15		T2	58		T3	35033

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51947093	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	79162601	1		T1	107907		T2	585947		T3	92707

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	344708	1		T3	367		T4	193		T5	174
valid_sources[0x01]	345820	1		T3	393		T4	180		T5	160
valid_sources[0x02]	346228	1		T3	357		T4	176		T5	194
valid_sources[0x03]	346255	1		T3	404		T4	211		T5	187
valid_sources[0x04]	346179	1		T3	395		T4	209		T5	186
valid_sources[0x05]	349432	1		T3	378		T4	210		T5	169
valid_sources[0x06]	344780	1		T3	396		T4	207		T5	189
valid_sources[0x07]	345279	1		T3	363		T4	185		T5	210
valid_sources[0x08]	345362	1		T3	383		T4	147		T5	177
valid_sources[0x09]	345588	1		T3	370		T4	202		T5	163
valid_sources[0x0a]	345404	1		T3	412		T4	164		T5	179
valid_sources[0x0b]	869268	1		T3	406		T4	224		T5	186
valid_sources[0x0c]	347025	1		T3	361		T4	208		T5	162
valid_sources[0x0d]	345479	1		T3	395		T4	196		T5	180
valid_sources[0x0e]	638181	1		T3	379		T4	238		T5	179
valid_sources[0x0f]	344354	1		T3	380		T4	149		T5	153
valid_sources[0x10]	2128232	1		T3	388		T4	184		T5	207
valid_sources[0x11]	868849	1		T3	441		T4	185		T5	183
valid_sources[0x12]	344624	1		T3	381		T4	181		T5	179
valid_sources[0x13]	343330	1		T3	390		T4	186		T5	196
valid_sources[0x14]	345944	1		T3	373		T4	176		T5	160
valid_sources[0x15]	367863	1		T3	393		T4	200		T5	158
valid_sources[0x16]	343301	1		T3	402		T4	179		T5	199
valid_sources[0x17]	345120	1		T3	367		T4	147		T5	186
valid_sources[0x18]	365158	1		T3	398		T4	205		T5	181
valid_sources[0x19]	346328	1		T3	372		T4	217		T5	168
valid_sources[0x1a]	345350	1		T3	355		T4	165		T5	210
valid_sources[0x1b]	344585	1		T3	406		T4	210		T5	181
valid_sources[0x1c]	347209	1		T3	400		T4	141		T5	183
valid_sources[0x1d]	1060822	1		T3	396		T4	192		T5	158
valid_sources[0x1e]	343656	1		T3	393		T4	209		T5	170
valid_sources[0x1f]	342436	1		T3	400		T4	213		T5	166
valid_sources[0x20]	346243	1		T3	387		T4	162		T5	170
valid_sources[0x21]	346973	1		T3	383		T4	214		T5	179
valid_sources[0x22]	397549	1		T3	439		T4	210		T5	168
valid_sources[0x23]	523808	1		T1	179454		T3	389		T4	204
valid_sources[0x24]	344357	1		T3	362		T4	209		T5	170
valid_sources[0x25]	347326	1		T3	384		T4	166		T5	177
valid_sources[0x26]	345888	1		T3	405		T4	185		T5	197
valid_sources[0x27]	428890	1		T3	402		T4	178		T5	200
valid_sources[0x28]	344189	1		T3	393		T4	203		T5	190
valid_sources[0x29]	344728	1		T3	422		T4	229		T5	165
valid_sources[0x2a]	342821	1		T3	393		T4	211		T5	162
valid_sources[0x2b]	805954	1		T3	374		T4	205		T5	157
valid_sources[0x2c]	346530	1		T3	394		T4	219		T5	194
valid_sources[0x2d]	518218	1		T3	391		T4	218		T5	181
valid_sources[0x2e]	392941	1		T3	396		T4	198		T5	171
valid_sources[0x2f]	344087	1		T3	388		T4	153		T5	187
valid_sources[0x30]	1729714	1		T3	400		T4	224		T5	162
valid_sources[0x31]	346366	1		T3	363		T4	170		T5	167
valid_sources[0x32]	344837	1		T3	415		T4	160		T5	173
valid_sources[0x33]	345707	1		T3	403		T4	214		T5	174
valid_sources[0x34]	343368	1		T3	418		T4	183		T5	160
valid_sources[0x35]	990895	1		T3	368		T4	171		T5	181
valid_sources[0x36]	344533	1		T3	428		T4	214		T5	187
valid_sources[0x37]	346387	1		T3	383		T4	179		T5	186
valid_sources[0x38]	344825	1		T3	368		T4	192		T5	173
valid_sources[0x39]	345365	1		T3	365		T4	176		T5	180
valid_sources[0x3a]	344546	1		T3	393		T4	166		T5	193
valid_sources[0x3b]	2824775	1		T3	390		T4	239		T5	171
valid_sources[0x3c]	346927	1		T3	398		T4	228		T5	149
valid_sources[0x3d]	1844026	1		T3	384		T4	213		T5	205
valid_sources[0x3e]	350958	1		T3	360		T4	173		T5	203
valid_sources[0x3f]	344781	1		T3	419		T4	195		T5	164
valid_sources[0x40]	602342	1		T3	394		T4	190		T5	190
valid_sources[0x41]	346016	1		T3	367		T4	220		T5	169
valid_sources[0x42]	344638	1		T3	424		T4	175		T5	189
valid_sources[0x43]	344867	1		T3	386		T4	172		T5	174
valid_sources[0x44]	346513	1		T3	384		T4	181		T5	163
valid_sources[0x45]	344259	1		T3	371		T4	253		T5	174
valid_sources[0x46]	347540	1		T3	396		T4	192		T5	207
valid_sources[0x47]	346561	1		T3	414		T4	171		T5	162
valid_sources[0x48]	343075	1		T3	382		T4	174		T5	199
valid_sources[0x49]	362131	1		T3	391		T4	189		T5	169
valid_sources[0x4a]	346235	1		T3	385		T4	158		T5	161
valid_sources[0x4b]	343828	1		T3	392		T4	188		T5	196
valid_sources[0x4c]	346718	1		T3	390		T4	165		T5	159
valid_sources[0x4d]	344942	1		T3	416		T4	189		T5	174
valid_sources[0x4e]	359584	1		T3	400		T4	228		T5	191
valid_sources[0x4f]	345565	1		T3	407		T4	167		T5	177
valid_sources[0x50]	342726	1		T3	395		T4	173		T5	187
valid_sources[0x51]	549803	1		T3	365		T4	186		T5	180
valid_sources[0x52]	343813	1		T3	361		T4	180		T5	167
valid_sources[0x53]	345334	1		T3	351		T4	167		T5	151
valid_sources[0x54]	344438	1		T3	374		T4	218		T5	181
valid_sources[0x55]	343278	1		T3	400		T4	208		T5	171
valid_sources[0x56]	348031	1		T3	401		T4	154		T5	176
valid_sources[0x57]	345909	1		T3	382		T4	184		T5	193
valid_sources[0x58]	345335	1		T3	358		T4	205		T5	164
valid_sources[0x59]	344405	1		T3	355		T4	155		T5	179
valid_sources[0x5a]	460801	1		T3	358		T4	186		T5	195
valid_sources[0x5b]	346381	1		T3	393		T4	198		T5	188
valid_sources[0x5c]	503912	1		T3	391		T4	211		T5	202
valid_sources[0x5d]	494079	1		T3	360		T4	205		T5	180
valid_sources[0x5e]	345453	1		T3	384		T4	162		T5	199
valid_sources[0x5f]	348071	1		T3	391		T4	182		T5	167
valid_sources[0x60]	347286	1		T3	392		T4	188		T5	178
valid_sources[0x61]	345736	1		T3	360		T4	192		T5	178
valid_sources[0x62]	344895	1		T3	379		T4	204		T5	184
valid_sources[0x63]	344526	1		T3	376		T4	218		T5	170
valid_sources[0x64]	343962	1		T3	379		T4	180		T5	182
valid_sources[0x65]	342473	1		T3	373		T4	224		T5	171
valid_sources[0x66]	345351	1		T3	404		T4	179		T5	186
valid_sources[0x67]	349372	1		T3	389		T4	178		T5	158
valid_sources[0x68]	543930	1		T3	361		T4	167		T5	171
valid_sources[0x69]	345700	1		T3	359		T4	147		T5	205
valid_sources[0x6a]	342658	1		T3	424		T4	198		T5	186
valid_sources[0x6b]	343060	1		T3	397		T4	186		T5	179
valid_sources[0x6c]	344991	1		T3	402		T4	185		T5	176
valid_sources[0x6d]	342702	1		T3	376		T4	158		T5	200
valid_sources[0x6e]	346782	1		T3	402		T4	186		T5	182
valid_sources[0x6f]	356039	1		T3	363		T4	174		T5	161
valid_sources[0x70]	344758	1		T3	368		T4	197		T5	189
valid_sources[0x71]	574384	1		T3	364		T4	186		T5	192
valid_sources[0x72]	345071	1		T3	401		T4	183		T5	176
valid_sources[0x73]	385088	1		T3	361		T4	212		T5	172
valid_sources[0x74]	345610	1		T3	387		T4	173		T5	165
valid_sources[0x75]	346305	1		T3	402		T4	171		T5	172
valid_sources[0x76]	4343644	1		T3	370		T4	206		T5	196
valid_sources[0x77]	343039	1		T3	337		T4	136		T5	180
valid_sources[0x78]	344405	1		T3	403		T4	201		T5	167
valid_sources[0x79]	344628	1		T3	395		T4	153		T5	196
valid_sources[0x7a]	346067	1		T3	406		T4	180		T5	171
valid_sources[0x7b]	347610	1		T3	415		T4	223		T5	189
valid_sources[0x7c]	345754	1		T3	399		T4	203		T5	195
valid_sources[0x7d]	343509	1		T3	401		T4	182		T5	161
valid_sources[0x7e]	373398	1		T3	389		T4	176		T5	164
valid_sources[0x7f]	345275	1		T3	378		T4	174		T5	157
valid_sources[0x80]	345429	1		T3	369		T4	200		T5	187

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65223503

1

T1

89744

T2

488175

T3

25908

values[0x0]

all_enables

biggest_size

427336

1

T1

14

T2

30

T3

31554

values[0x1]

all_enables

biggest_size

426788

1

T1

8

T2

28

T3

31131