SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_timer_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 133347984 | 0 | T1 | 179454 | T2 | 977841 | T3 | 271338 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 133347705 | 1 | T1 | 179454 | T2 | 977841 | T3 | 271338 | |||
values[1] | 31 | 1 | T26 | 2 | T28 | 4 | T85 | 3 | |||
values[2] | 4 | 1 | T86 | 1 | T87 | 2 | T88 | 1 | |||
values[3] | 139 | 1 | T26 | 8 | T27 | 3 | T28 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 133347701 | 1 | T1 | 179454 | T2 | 977841 | T3 | 271338 | |||
values[1] | 21 | 1 | T27 | 1 | T89 | 2 | T86 | 2 | |||
values[2] | 6 | 1 | T27 | 1 | T85 | 1 | T87 | 2 | |||
values[3] | 150 | 1 | T26 | 8 | T27 | 4 | T28 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 133347554 | 1 | T1 | 179454 | T2 | 977841 | T3 | 271338 | |||
auto[TlIntgErrCmd] | 147 | 1 | T26 | 7 | T27 | 1 | T28 | 12 | |||
auto[TlIntgErrData] | 151 | 1 | T26 | 5 | T27 | 5 | T28 | 6 | |||
auto[TlIntgErrBoth] | 132 | 1 | T26 | 8 | T27 | 4 | T28 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |