Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1475631	0	0
cfg0_rd_A	2147483647	6041	0	0
compare_lower0_0_rd_A	2147483647	6512	0	0
compare_upper0_0_rd_A	2147483647	5810	0	0
ctrl_rd_A	2147483647	6034	0	0
intr_enable0_rd_A	2147483647	7606	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1475631	0	0
T3	370064	112750	0	0
T4	826419	0	0	0
T5	215100	53940	0	0
T6	220152	0	0	0
T7	136509	0	0	0
T8	145647	0	0	0
T9	805312	0	0	0
T10	738503	0	0	0
T11	0	112326	0	0
T32	0	409938	0	0
T33	0	167599	0	0
T34	0	165703	0	0
T35	0	134092	0	0
T36	0	98821	0	0
T37	0	72342	0	0
T38	0	86053	0	0
T39	127236	0	0	0
T40	399918	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6041	0	0
T5	215100	456	0	0
T6	220152	0	0	0
T7	136509	0	0	0
T8	145647	0	0	0
T9	805312	0	0	0
T10	738503	0	0	0
T26	0	36	0	0
T29	0	2	0	0
T33	0	1613	0	0
T34	0	1680	0	0
T39	127236	0	0	0
T40	399918	0	0	0
T41	0	367	0	0
T42	0	16	0	0
T43	0	47	0	0
T44	0	21	0	0
T45	0	41	0	0
T46	262777	0	0	0
T47	142758	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6512	0	0
T5	215100	528	0	0
T6	220152	0	0	0
T7	136509	0	0	0
T8	145647	0	0	0
T9	805312	0	0	0
T10	738503	0	0	0
T26	0	53	0	0
T29	0	7	0	0
T33	0	2053	0	0
T34	0	1856	0	0
T39	127236	0	0	0
T40	399918	0	0	0
T41	0	355	0	0
T42	0	19	0	0
T43	0	47	0	0
T44	0	22	0	0
T46	262777	0	0	0
T47	142758	0	0	0
T48	0	7	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5810	0	0
T5	215100	572	0	0
T6	220152	0	0	0
T7	136509	0	0	0
T8	145647	0	0	0
T9	805312	0	0	0
T10	738503	0	0	0
T26	0	37	0	0
T29	0	8	0	0
T33	0	1630	0	0
T34	0	1636	0	0
T39	127236	0	0	0
T40	399918	0	0	0
T41	0	261	0	0
T42	0	3	0	0
T43	0	44	0	0
T46	262777	0	0	0
T47	142758	0	0	0
T48	0	7	0	0
T49	0	12	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6034	0	0
T5	215100	524	0	0
T6	220152	0	0	0
T7	136509	0	0	0
T8	145647	0	0	0
T9	805312	0	0	0
T10	738503	0	0	0
T26	0	25	0	0
T29	0	29	0	0
T33	0	1871	0	0
T34	0	1782	0	0
T39	127236	0	0	0
T40	399918	0	0	0
T41	0	259	0	0
T42	0	18	0	0
T43	0	49	0	0
T46	262777	0	0	0
T47	142758	0	0	0
T48	0	2	0	0
T49	0	17	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7606	0	0
T5	215100	743	0	0
T6	220152	0	0	0
T7	136509	0	0	0
T8	145647	0	0	0
T9	805312	0	0	0
T10	738503	0	0	0
T33	0	2058	0	0
T34	0	1914	0	0
T39	127236	0	0	0
T40	399918	0	0	0
T46	262777	0	0	0
T47	142758	0	0	0
T50	0	35	0	0
T51	0	19	0	0
T52	0	23	0	0
T53	0	48	0	0
T54	0	60	0	0
T55	0	60	0	0
T56	0	44	0	0