Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67898598	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	69639422	1		T1	105075		T2	421401		T3	477577

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136038456	1		T1	210347		T2	842762		T3	955094
values[0x0]	712997	1		T1	109		T2	31		T3	137
values[0x1]	786567	1		T1	101		T2	19		T3	153

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54221272	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	83316748	1		T1	126214		T2	506152		T3	573677

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	438212	1		T2	3360		T3	3732		T4	1814
valid_sources[0x01]	424033	1		T2	3313		T3	3671		T4	1857
valid_sources[0x02]	431115	1		T2	3275		T3	3780		T4	1460
valid_sources[0x03]	431582	1		T2	3274		T3	3712		T4	1723
valid_sources[0x04]	436186	1		T2	3388		T3	3760		T4	1739
valid_sources[0x05]	430283	1		T2	3203		T3	3658		T4	1685
valid_sources[0x06]	429998	1		T2	3343		T3	3763		T4	1461
valid_sources[0x07]	432624	1		T2	3324		T3	3739		T4	1633
valid_sources[0x08]	432134	1		T2	3260		T3	3667		T4	1613
valid_sources[0x09]	537423	1		T2	3350		T3	3703		T4	1783
valid_sources[0x0a]	429626	1		T2	3200		T3	3746		T4	1610
valid_sources[0x0b]	430431	1		T2	3379		T3	3767		T4	1854
valid_sources[0x0c]	432045	1		T2	3319		T3	3775		T4	1682
valid_sources[0x0d]	428912	1		T2	3273		T3	3876		T4	1727
valid_sources[0x0e]	433513	1		T2	3275		T3	3739		T4	1638
valid_sources[0x0f]	431757	1		T2	3333		T3	3772		T4	1723
valid_sources[0x10]	429912	1		T2	3262		T3	3700		T4	1804
valid_sources[0x11]	427164	1		T2	3272		T3	3785		T4	1640
valid_sources[0x12]	502720	1		T2	3362		T3	3687		T4	1804
valid_sources[0x13]	430357	1		T2	3260		T3	3694		T4	1855
valid_sources[0x14]	433139	1		T2	3348		T3	3763		T4	1535
valid_sources[0x15]	433281	1		T2	3344		T3	3775		T4	1739
valid_sources[0x16]	690153	1		T2	3316		T3	3772		T4	1569
valid_sources[0x17]	433367	1		T2	3344		T3	3742		T4	1598
valid_sources[0x18]	607886	1		T2	3235		T3	3734		T4	1651
valid_sources[0x19]	2815671	1		T2	3244		T3	3688		T4	1652
valid_sources[0x1a]	429759	1		T2	3353		T3	3735		T4	1468
valid_sources[0x1b]	433466	1		T2	3265		T3	3742		T4	1475
valid_sources[0x1c]	433697	1		T2	3252		T3	3695		T4	1746
valid_sources[0x1d]	936809	1		T2	3342		T3	3814		T4	1573
valid_sources[0x1e]	433288	1		T2	3211		T3	3718		T4	1690
valid_sources[0x1f]	431758	1		T2	3382		T3	3622		T4	1543
valid_sources[0x20]	429591	1		T2	3216		T3	3766		T4	1691
valid_sources[0x21]	791242	1		T2	3375		T3	3669		T4	1741
valid_sources[0x22]	3148766	1		T2	3310		T3	3796		T4	1751
valid_sources[0x23]	429883	1		T2	3236		T3	3791		T4	1571
valid_sources[0x24]	455374	1		T2	3363		T3	3776		T4	1800
valid_sources[0x25]	427064	1		T2	3250		T3	3786		T4	1412
valid_sources[0x26]	431024	1		T2	3272		T3	3643		T4	1545
valid_sources[0x27]	436566	1		T2	3255		T3	3624		T4	1584
valid_sources[0x28]	432039	1		T2	3399		T3	3824		T4	1640
valid_sources[0x29]	438329	1		T2	3314		T3	3713		T4	1661
valid_sources[0x2a]	430640	1		T2	3217		T3	3921		T4	1695
valid_sources[0x2b]	430614	1		T2	3249		T3	3815		T4	1641
valid_sources[0x2c]	430956	1		T2	3300		T3	3754		T4	1513
valid_sources[0x2d]	433872	1		T2	3321		T3	3702		T4	1678
valid_sources[0x2e]	434451	1		T2	3334		T3	3741		T4	1631
valid_sources[0x2f]	430523	1		T2	3276		T3	3661		T4	1886
valid_sources[0x30]	521054	1		T2	3346		T3	3654		T4	1589
valid_sources[0x31]	508289	1		T2	3260		T3	3748		T4	1595
valid_sources[0x32]	431744	1		T2	3180		T3	3775		T4	1585
valid_sources[0x33]	434022	1		T2	3264		T3	3743		T4	1710
valid_sources[0x34]	426421	1		T2	3195		T3	3657		T4	1690
valid_sources[0x35]	433175	1		T2	3296		T3	3680		T4	1736
valid_sources[0x36]	450080	1		T2	3293		T3	3682		T4	1747
valid_sources[0x37]	435024	1		T2	3356		T3	3756		T4	1626
valid_sources[0x38]	434725	1		T2	3342		T3	3715		T4	1815
valid_sources[0x39]	433595	1		T2	3245		T3	3602		T4	1737
valid_sources[0x3a]	430663	1		T2	3173		T3	3830		T4	1538
valid_sources[0x3b]	433333	1		T2	3225		T3	3768		T4	1937
valid_sources[0x3c]	434532	1		T2	3302		T3	3672		T4	1661
valid_sources[0x3d]	476722	1		T2	3306		T3	3812		T4	1571
valid_sources[0x3e]	4190279	1		T2	3312		T3	3695		T4	1457
valid_sources[0x3f]	430537	1		T2	3292		T3	3672		T4	1705
valid_sources[0x40]	429963	1		T2	3344		T3	3781		T4	1782
valid_sources[0x41]	428537	1		T2	3257		T3	3794		T4	1830
valid_sources[0x42]	432406	1		T2	3265		T3	3801		T4	1548
valid_sources[0x43]	432560	1		T2	3260		T3	3705		T4	1451
valid_sources[0x44]	432850	1		T2	3384		T3	3673		T4	1947
valid_sources[0x45]	434401	1		T2	3389		T3	3822		T4	1690
valid_sources[0x46]	452635	1		T2	3351		T3	3831		T4	1552
valid_sources[0x47]	433206	1		T2	3221		T3	3829		T4	1869
valid_sources[0x48]	433218	1		T2	3268		T3	3826		T4	1932
valid_sources[0x49]	469580	1		T2	3327		T3	3847		T4	1736
valid_sources[0x4a]	482883	1		T2	3277		T3	3792		T4	1615
valid_sources[0x4b]	433098	1		T2	3259		T3	3729		T4	1731
valid_sources[0x4c]	431624	1		T2	3359		T3	3768		T4	1695
valid_sources[0x4d]	433759	1		T2	3316		T3	3756		T4	1495
valid_sources[0x4e]	432256	1		T2	3273		T3	3831		T4	1645
valid_sources[0x4f]	431275	1		T2	3220		T3	3769		T4	1768
valid_sources[0x50]	446794	1		T2	3315		T3	3810		T4	1603
valid_sources[0x51]	428928	1		T2	3316		T3	3612		T4	1645
valid_sources[0x52]	2438659	1		T2	3261		T3	3662		T4	1766
valid_sources[0x53]	431296	1		T2	3334		T3	3788		T4	1718
valid_sources[0x54]	3199014	1		T2	3251		T3	3708		T4	1614
valid_sources[0x55]	431470	1		T2	3387		T3	3669		T4	1630
valid_sources[0x56]	438029	1		T2	3366		T3	3741		T4	1632
valid_sources[0x57]	432695	1		T2	3204		T3	3702		T4	1409
valid_sources[0x58]	435201	1		T2	3240		T3	3701		T4	1742
valid_sources[0x59]	435315	1		T2	3302		T3	3601		T4	1878
valid_sources[0x5a]	431316	1		T2	3385		T3	3728		T4	1632
valid_sources[0x5b]	452757	1		T2	3301		T3	3690		T4	1429
valid_sources[0x5c]	431341	1		T2	3210		T3	3831		T4	1720
valid_sources[0x5d]	433585	1		T2	3410		T3	3697		T4	1718
valid_sources[0x5e]	428400	1		T2	3283		T3	3784		T4	1662
valid_sources[0x5f]	502511	1		T2	3294		T3	3688		T4	1659
valid_sources[0x60]	431126	1		T2	3277		T3	3723		T4	1514
valid_sources[0x61]	479289	1		T2	3283		T3	3786		T4	1586
valid_sources[0x62]	435739	1		T2	3332		T3	3614		T4	1775
valid_sources[0x63]	438872	1		T2	3333		T3	3695		T4	1508
valid_sources[0x64]	428759	1		T2	3312		T3	3665		T4	1561
valid_sources[0x65]	432291	1		T2	3316		T3	3711		T4	1525
valid_sources[0x66]	430523	1		T2	3188		T3	3763		T4	1808
valid_sources[0x67]	430935	1		T2	3178		T3	3707		T4	1725
valid_sources[0x68]	431972	1		T2	3274		T3	3686		T4	1614
valid_sources[0x69]	431475	1		T2	3305		T3	3692		T4	1623
valid_sources[0x6a]	437020	1		T2	3342		T3	3778		T4	1609
valid_sources[0x6b]	434910	1		T2	3255		T3	3747		T4	1733
valid_sources[0x6c]	431610	1		T2	3193		T3	3767		T4	1782
valid_sources[0x6d]	640702	1		T2	3261		T3	3739		T4	1527
valid_sources[0x6e]	430442	1		T2	3325		T3	3615		T4	1577
valid_sources[0x6f]	434288	1		T2	3249		T3	3695		T4	1646
valid_sources[0x70]	432051	1		T2	3337		T3	3782		T4	1799
valid_sources[0x71]	430025	1		T2	3179		T3	3779		T4	1704
valid_sources[0x72]	428618	1		T2	3223		T3	3775		T4	1592
valid_sources[0x73]	491834	1		T2	3295		T3	3660		T4	1765
valid_sources[0x74]	642545	1		T2	3234		T3	3827		T4	1524
valid_sources[0x75]	433415	1		T2	3346		T3	3744		T4	1857
valid_sources[0x76]	431586	1		T2	3265		T3	3755		T4	1727
valid_sources[0x77]	432347	1		T2	3231		T3	3791		T4	1698
valid_sources[0x78]	431897	1		T2	3324		T3	3726		T4	1693
valid_sources[0x79]	430915	1		T2	3262		T3	3760		T4	1681
valid_sources[0x7a]	438424	1		T2	3266		T3	3654		T4	1821
valid_sources[0x7b]	433379	1		T2	3337		T3	3764		T4	1698
valid_sources[0x7c]	429683	1		T2	3354		T3	3657		T4	1636
valid_sources[0x7d]	430929	1		T2	3231		T3	3689		T4	1732
valid_sources[0x7e]	428486	1		T2	3291		T3	3809		T4	1741
valid_sources[0x7f]	810791	1		T2	3408		T3	3717		T4	1501
valid_sources[0x80]	432567	1		T2	3250		T3	3675		T4	1823

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

68242132

1

T1

104962

T2

421365

T3

477406

values[0x0]

all_enables

biggest_size

699744

1

T1

62

T2

25

T3

87

values[0x1]

all_enables

biggest_size

697546

1

T1

51

T2

11

T3

84