Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2440787	0	0
cfg0_rd_A	2147483647	10387	0	0
compare_lower0_0_rd_A	2147483647	10774	0	0
compare_upper0_0_rd_A	2147483647	9804	0	0
ctrl_rd_A	2147483647	9966	0	0
intr_enable0_rd_A	2147483647	12486	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2440787	0	0
T12	229835	59923	0	0
T13	0	152543	0	0
T14	0	267017	0	0
T15	4420	0	0	0
T30	0	61306	0	0
T31	0	309921	0	0
T32	0	113329	0	0
T33	0	245545	0	0
T34	0	100429	0	0
T35	0	36972	0	0
T36	0	183100	0	0
T37	3562	0	0	0
T38	125003	0	0	0
T39	597136	0	0	0
T40	263922	0	0	0
T41	513131	0	0	0
T42	890096	0	0	0
T43	112505	0	0	0
T44	152775	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10387	0	0
T12	229835	361	0	0
T14	0	2812	0	0
T15	4420	0	0	0
T28	0	29	0	0
T29	0	36	0	0
T31	0	3152	0	0
T32	0	1222	0	0
T37	3562	0	0	0
T38	125003	0	0	0
T39	597136	0	0	0
T40	263922	0	0	0
T41	513131	0	0	0
T42	890096	0	0	0
T43	112505	0	0	0
T44	152775	0	0	0
T45	0	293	0	0
T46	0	775	0	0
T47	0	254	0	0
T48	0	83	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10774	0	0
T12	229835	308	0	0
T14	0	2903	0	0
T15	4420	0	0	0
T28	0	32	0	0
T29	0	63	0	0
T31	0	3166	0	0
T32	0	1374	0	0
T37	3562	0	0	0
T38	125003	0	0	0
T39	597136	0	0	0
T40	263922	0	0	0
T41	513131	0	0	0
T42	890096	0	0	0
T43	112505	0	0	0
T44	152775	0	0	0
T45	0	354	0	0
T46	0	1096	0	0
T47	0	304	0	0
T49	0	19	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9804	0	0
T12	229835	420	0	0
T14	0	2655	0	0
T15	4420	0	0	0
T28	0	16	0	0
T29	0	48	0	0
T31	0	3091	0	0
T32	0	1116	0	0
T37	3562	0	0	0
T38	125003	0	0	0
T39	597136	0	0	0
T40	263922	0	0	0
T41	513131	0	0	0
T42	890096	0	0	0
T43	112505	0	0	0
T44	152775	0	0	0
T45	0	273	0	0
T46	0	705	0	0
T47	0	333	0	0
T48	0	37	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	9966	0	0
T12	229835	331	0	0
T14	0	2855	0	0
T15	4420	0	0	0
T28	0	26	0	0
T29	0	79	0	0
T31	0	3255	0	0
T32	0	1066	0	0
T37	3562	0	0	0
T38	125003	0	0	0
T39	597136	0	0	0
T40	263922	0	0	0
T41	513131	0	0	0
T42	890096	0	0	0
T43	112505	0	0	0
T44	152775	0	0	0
T45	0	316	0	0
T46	0	772	0	0
T47	0	229	0	0
T49	0	4	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12486	0	0
T1	392417	120	0	0
T2	159027	0	0	0
T3	542389	70	0	0
T4	153492	0	0	0
T5	699842	0	0	0
T6	127358	0	0	0
T7	120842	0	0	0
T8	7478	0	0	0
T9	430669	0	0	0
T10	244946	0	0	0
T12	0	417	0	0
T14	0	3394	0	0
T31	0	3710	0	0
T32	0	1349	0	0
T39	0	60	0	0
T45	0	405	0	0
T50	0	43	0	0
T51	0	11	0	0