Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61266487	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	62576985	1		T1	172787		T2	71718		T3	97627

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	122695253	1		T1	345786		T2	143375		T3	33056
values[0x0]	546023	1		T1	28		T2	8		T3	35191
values[0x1]	602196	1		T1	22		T2	10		T3	39287

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48932802	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	74910670	1		T1	207550		T2	86087		T3	101663

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	388587	1		T1	1319		T3	429		T7	160
valid_sources[0x01]	385716	1		T1	1298		T3	408		T7	171
valid_sources[0x02]	386150	1		T1	1305		T3	408		T4	11
valid_sources[0x03]	390490	1		T1	1491		T3	441		T4	7
valid_sources[0x04]	390791	1		T1	1306		T3	408		T7	163
valid_sources[0x05]	668174	1		T1	1305		T3	516		T4	5
valid_sources[0x06]	386894	1		T1	1280		T3	382		T6	1
valid_sources[0x07]	390514	1		T1	1397		T3	444		T4	10
valid_sources[0x08]	388664	1		T1	1376		T3	400		T4	8
valid_sources[0x09]	390023	1		T1	1335		T3	507		T4	2
valid_sources[0x0a]	390774	1		T1	1347		T3	441		T7	183
valid_sources[0x0b]	390662	1		T1	1449		T3	393		T4	6
valid_sources[0x0c]	391616	1		T1	1393		T3	283		T6	1
valid_sources[0x0d]	387223	1		T1	1371		T3	327		T4	2
valid_sources[0x0e]	388497	1		T1	1328		T3	460		T6	2
valid_sources[0x0f]	384966	1		T1	1304		T3	467		T4	8
valid_sources[0x10]	387554	1		T1	1341		T3	464		T4	8
valid_sources[0x11]	388323	1		T1	1302		T3	415		T4	11
valid_sources[0x12]	401269	1		T1	1457		T3	398		T4	2
valid_sources[0x13]	385121	1		T1	1286		T3	378		T6	4
valid_sources[0x14]	444702	1		T1	1283		T3	378		T4	7
valid_sources[0x15]	388040	1		T1	1356		T3	428		T4	6
valid_sources[0x16]	390548	1		T1	1392		T3	380		T4	1
valid_sources[0x17]	397456	1		T1	1389		T3	525		T6	2
valid_sources[0x18]	389142	1		T1	1376		T3	355		T4	3
valid_sources[0x19]	388959	1		T1	1444		T3	406		T6	2
valid_sources[0x1a]	389850	1		T1	1401		T3	597		T4	1
valid_sources[0x1b]	742801	1		T1	1258		T3	401		T4	4
valid_sources[0x1c]	403108	1		T1	1286		T3	359		T7	189
valid_sources[0x1d]	396587	1		T1	1380		T3	282		T4	2
valid_sources[0x1e]	386757	1		T1	1417		T3	364		T6	2
valid_sources[0x1f]	720067	1		T1	1430		T3	372		T4	9
valid_sources[0x20]	386136	1		T1	1415		T3	336		T7	165
valid_sources[0x21]	387392	1		T1	1396		T3	476		T7	162
valid_sources[0x22]	386179	1		T1	1350		T3	459		T6	1
valid_sources[0x23]	970538	1		T1	1410		T3	377		T4	1
valid_sources[0x24]	396481	1		T1	1344		T3	424		T4	3
valid_sources[0x25]	387588	1		T1	1369		T3	414		T6	1
valid_sources[0x26]	386470	1		T1	1291		T3	448		T7	184
valid_sources[0x27]	384294	1		T1	1408		T3	397		T6	2
valid_sources[0x28]	443757	1		T1	1449		T3	346		T4	4
valid_sources[0x29]	389243	1		T1	1348		T3	326		T4	6
valid_sources[0x2a]	406964	1		T1	1324		T3	417		T4	1
valid_sources[0x2b]	387541	1		T1	1355		T3	398		T7	163
valid_sources[0x2c]	386527	1		T1	1313		T3	478		T6	2
valid_sources[0x2d]	387062	1		T1	1309		T3	564		T4	8
valid_sources[0x2e]	394569	1		T1	1379		T3	410		T4	5
valid_sources[0x2f]	415487	1		T1	1335		T3	471		T4	8
valid_sources[0x30]	385838	1		T1	1316		T3	468		T7	165
valid_sources[0x31]	386973	1		T1	1265		T3	520		T6	3
valid_sources[0x32]	389043	1		T1	1350		T3	359		T6	4
valid_sources[0x33]	384321	1		T1	1347		T3	313		T4	2
valid_sources[0x34]	443436	1		T1	1302		T3	335		T4	2
valid_sources[0x35]	391192	1		T1	1383		T3	379		T4	8
valid_sources[0x36]	388174	1		T1	1304		T3	339		T4	6
valid_sources[0x37]	386732	1		T1	1335		T3	505		T4	4
valid_sources[0x38]	389355	1		T1	1328		T3	375		T7	154
valid_sources[0x39]	384649	1		T1	1379		T3	537		T4	1
valid_sources[0x3a]	392317	1		T1	1364		T3	466		T4	5
valid_sources[0x3b]	397534	1		T1	1258		T3	321		T4	1
valid_sources[0x3c]	387456	1		T1	1318		T3	430		T6	4
valid_sources[0x3d]	388450	1		T1	1334		T3	398		T4	2
valid_sources[0x3e]	389935	1		T1	1376		T3	505		T4	5
valid_sources[0x3f]	384265	1		T1	1318		T3	278		T6	1
valid_sources[0x40]	389202	1		T1	1357		T3	471		T4	1
valid_sources[0x41]	428666	1		T1	1314		T3	363		T4	1
valid_sources[0x42]	389219	1		T1	1402		T3	459		T6	2
valid_sources[0x43]	384207	1		T1	1240		T3	392		T4	1
valid_sources[0x44]	388152	1		T1	1276		T3	493		T4	3
valid_sources[0x45]	387343	1		T1	1325		T3	447		T4	21
valid_sources[0x46]	389620	1		T1	1230		T3	424		T6	2
valid_sources[0x47]	388608	1		T1	1328		T3	263		T6	3
valid_sources[0x48]	955513	1		T1	1322		T3	450		T4	4
valid_sources[0x49]	795595	1		T1	1321		T3	385		T4	5
valid_sources[0x4a]	437617	1		T1	1416		T3	643		T4	15
valid_sources[0x4b]	401553	1		T1	1397		T3	454		T4	4
valid_sources[0x4c]	940093	1		T1	1350		T3	276		T4	8
valid_sources[0x4d]	391502	1		T1	1375		T3	308		T4	1
valid_sources[0x4e]	388282	1		T1	1396		T3	346		T4	1
valid_sources[0x4f]	393165	1		T1	1421		T3	492		T4	4
valid_sources[0x50]	425811	1		T1	1318		T3	432		T6	1
valid_sources[0x51]	385470	1		T1	1366		T3	552		T6	2
valid_sources[0x52]	392224	1		T1	1391		T3	487		T4	1
valid_sources[0x53]	384389	1		T1	1349		T3	291		T6	2
valid_sources[0x54]	798228	1		T1	1345		T3	574		T4	7
valid_sources[0x55]	389206	1		T1	1327		T3	388		T4	9
valid_sources[0x56]	388964	1		T1	1368		T3	405		T4	1
valid_sources[0x57]	860535	1		T1	1508		T3	391		T6	1
valid_sources[0x58]	390375	1		T1	1325		T3	317		T4	1
valid_sources[0x59]	383015	1		T1	1435		T3	553		T4	8
valid_sources[0x5a]	387551	1		T1	1226		T3	380		T7	172
valid_sources[0x5b]	404101	1		T1	1336		T3	555		T4	6
valid_sources[0x5c]	412796	1		T1	1357		T3	465		T4	3
valid_sources[0x5d]	393935	1		T1	1237		T3	237		T4	2
valid_sources[0x5e]	388995	1		T1	1449		T3	406		T4	5
valid_sources[0x5f]	385836	1		T1	1334		T3	487		T4	2
valid_sources[0x60]	488229	1		T1	1385		T3	439		T4	4
valid_sources[0x61]	386709	1		T1	1225		T3	282		T4	5
valid_sources[0x62]	915029	1		T1	1314		T3	534		T6	2
valid_sources[0x63]	385404	1		T1	1400		T3	236		T6	1
valid_sources[0x64]	388479	1		T1	1345		T3	328		T6	1
valid_sources[0x65]	400073	1		T1	1371		T3	493		T4	7
valid_sources[0x66]	397317	1		T1	1326		T3	410		T4	2
valid_sources[0x67]	385234	1		T1	1415		T3	432		T6	2
valid_sources[0x68]	387720	1		T1	1435		T3	383		T4	1
valid_sources[0x69]	388225	1		T1	1310		T3	522		T4	4
valid_sources[0x6a]	386446	1		T1	1274		T3	358		T4	1
valid_sources[0x6b]	386696	1		T1	1217		T3	364		T4	3
valid_sources[0x6c]	390674	1		T1	1334		T3	519		T7	167
valid_sources[0x6d]	683417	1		T1	1439		T3	492		T4	4
valid_sources[0x6e]	401669	1		T1	1385		T3	426		T6	1
valid_sources[0x6f]	390060	1		T1	1325		T3	366		T4	4
valid_sources[0x70]	388571	1		T1	1396		T3	496		T4	1
valid_sources[0x71]	388882	1		T1	1225		T3	319		T6	1
valid_sources[0x72]	390184	1		T1	1343		T3	290		T6	3
valid_sources[0x73]	387838	1		T1	1344		T3	432		T4	4
valid_sources[0x74]	386584	1		T1	1411		T3	504		T4	12
valid_sources[0x75]	487284	1		T1	1326		T3	387		T4	3
valid_sources[0x76]	386513	1		T1	1287		T3	453		T4	3
valid_sources[0x77]	807478	1		T1	1358		T3	504		T4	19
valid_sources[0x78]	388049	1		T1	1277		T3	462		T4	7
valid_sources[0x79]	389834	1		T1	1352		T3	338		T4	5
valid_sources[0x7a]	2051900	1		T1	1379		T3	340		T6	3
valid_sources[0x7b]	419475	1		T1	1447		T3	424		T4	3
valid_sources[0x7c]	386737	1		T1	1370		T3	336		T4	6
valid_sources[0x7d]	387619	1		T1	1372		T3	513		T4	13
valid_sources[0x7e]	389495	1		T1	1343		T3	513		T4	10
valid_sources[0x7f]	384530	1		T1	1378		T3	365		T6	1
valid_sources[0x80]	387258	1		T1	1326		T3	429		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61509277

1

T1

172754

T2

71705

T3

27637

values[0x0]

all_enables

biggest_size

535016

1

T1

19

T2

6

T3

34799

values[0x1]

all_enables

biggest_size

532692

1

T1

14

T2

7

T3

35191