Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1867651	0	0
cfg0_rd_A	2147483647	3274	0	0
compare_lower0_0_rd_A	2147483647	3453	0	0
compare_upper0_0_rd_A	2147483647	3052	0	0
ctrl_rd_A	2147483647	3077	0	0
intr_enable0_rd_A	2147483647	5091	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1867651	0	0
T3	349619	123437	0	0
T4	127229	0	0	0
T5	159425	0	0	0
T6	9151	0	0	0
T7	227795	0	0	0
T8	277778	0	0	0
T9	179772	0	0	0
T10	954119	0	0	0
T11	0	31661	0	0
T12	0	117638	0	0
T35	0	169315	0	0
T36	0	60356	0	0
T37	0	70697	0	0
T38	0	48649	0	0
T39	0	334726	0	0
T40	0	41436	0	0
T41	0	78298	0	0
T42	494497	0	0	0
T43	615150	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3274	0	0
T28	0	27	0	0
T38	191793	535	0	0
T40	0	449	0	0
T44	0	725	0	0
T45	0	285	0	0
T46	0	4	0	0
T47	0	66	0	0
T48	0	15	0	0
T49	0	16	0	0
T50	0	104	0	0
T51	590755	0	0	0
T52	112653	0	0	0
T53	152052	0	0	0
T54	600184	0	0	0
T55	247989	0	0	0
T56	668103	0	0	0
T57	657507	0	0	0
T58	644908	0	0	0
T59	712977	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3453	0	0
T28	0	18	0	0
T38	191793	540	0	0
T40	0	546	0	0
T44	0	920	0	0
T45	0	361	0	0
T47	0	32	0	0
T48	0	2	0	0
T49	0	11	0	0
T50	0	70	0	0
T51	590755	0	0	0
T52	112653	0	0	0
T53	152052	0	0	0
T54	600184	0	0	0
T55	247989	0	0	0
T56	668103	0	0	0
T57	657507	0	0	0
T58	644908	0	0	0
T59	712977	0	0	0
T60	0	3	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3052	0	0
T28	0	9	0	0
T38	191793	519	0	0
T40	0	366	0	0
T44	0	751	0	0
T45	0	280	0	0
T46	0	7	0	0
T47	0	34	0	0
T48	0	5	0	0
T49	0	1	0	0
T50	0	70	0	0
T51	590755	0	0	0
T52	112653	0	0	0
T53	152052	0	0	0
T54	600184	0	0	0
T55	247989	0	0	0
T56	668103	0	0	0
T57	657507	0	0	0
T58	644908	0	0	0
T59	712977	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3077	0	0
T28	0	31	0	0
T38	191793	526	0	0
T40	0	469	0	0
T44	0	704	0	0
T45	0	288	0	0
T46	0	5	0	0
T47	0	35	0	0
T48	0	2	0	0
T49	0	17	0	0
T50	0	73	0	0
T51	590755	0	0	0
T52	112653	0	0	0
T53	152052	0	0	0
T54	600184	0	0	0
T55	247989	0	0	0
T56	668103	0	0	0
T57	657507	0	0	0
T58	644908	0	0	0
T59	712977	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5091	0	0
T38	0	688	0	0
T40	0	735	0	0
T55	0	12	0	0
T61	311838	19	0	0
T62	0	44	0	0
T63	0	63	0	0
T64	0	114	0	0
T65	0	32	0	0
T66	0	62	0	0
T67	0	63	0	0
T68	415441	0	0	0
T69	379034	0	0	0
T70	122797	0	0	0
T71	215597	0	0	0
T72	121119	0	0	0
T73	335297	0	0	0
T74	107615	0	0	0
T75	215450	0	0	0
T76	817870	0	0	0