Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3241537	0	0
cfg0_rd_A	2147483647	4600	0	0
compare_lower0_0_rd_A	2147483647	4927	0	0
compare_upper0_0_rd_A	2147483647	4801	0	0
ctrl_rd_A	2147483647	4359	0	0
intr_enable0_rd_A	2147483647	5738	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3241537	0	0
T4	657703	271864	0	0
T5	110083	0	0	0
T6	163029	0	0	0
T7	122789	0	0	0
T8	106105	0	0	0
T9	863927	0	0	0
T10	129313	0	0	0
T12	0	154456	0	0
T13	0	137504	0	0
T34	0	247961	0	0
T35	0	179864	0	0
T36	0	174037	0	0
T37	0	149404	0	0
T38	0	113427	0	0
T39	0	130092	0	0
T40	0	69093	0	0
T41	236746	0	0	0
T42	158726	0	0	0
T43	186111	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4600	0	0
T28	0	82	0	0
T29	0	82	0	0
T35	651066	758	0	0
T38	0	515	0	0
T44	0	7	0	0
T45	0	19	0	0
T46	0	22	0	0
T47	0	674	0	0
T48	0	383	0	0
T49	0	8	0	0
T50	189203	0	0	0
T51	124016	0	0	0
T52	103070	0	0	0
T53	451255	0	0	0
T54	267562	0	0	0
T55	191604	0	0	0
T56	715654	0	0	0
T57	191053	0	0	0
T58	572789	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4927	0	0
T28	0	35	0	0
T29	0	54	0	0
T35	651066	1092	0	0
T38	0	827	0	0
T44	0	21	0	0
T45	0	36	0	0
T46	0	15	0	0
T47	0	681	0	0
T48	0	389	0	0
T50	189203	0	0	0
T51	124016	0	0	0
T52	103070	0	0	0
T53	451255	0	0	0
T54	267562	0	0	0
T55	191604	0	0	0
T56	715654	0	0	0
T57	191053	0	0	0
T58	572789	0	0	0
T59	0	8	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4801	0	0
T28	0	42	0	0
T29	0	77	0	0
T35	651066	1090	0	0
T38	0	638	0	0
T44	0	19	0	0
T45	0	27	0	0
T46	0	10	0	0
T47	0	654	0	0
T48	0	472	0	0
T49	0	4	0	0
T50	189203	0	0	0
T51	124016	0	0	0
T52	103070	0	0	0
T53	451255	0	0	0
T54	267562	0	0	0
T55	191604	0	0	0
T56	715654	0	0	0
T57	191053	0	0	0
T58	572789	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4359	0	0
T28	0	23	0	0
T29	0	80	0	0
T35	651066	852	0	0
T38	0	546	0	0
T44	0	14	0	0
T45	0	47	0	0
T46	0	9	0	0
T47	0	678	0	0
T48	0	388	0	0
T50	189203	0	0	0
T51	124016	0	0	0
T52	103070	0	0	0
T53	451255	0	0	0
T54	267562	0	0	0
T55	191604	0	0	0
T56	715654	0	0	0
T57	191053	0	0	0
T58	572789	0	0	0
T59	0	3	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5738	0	0
T11	466338	9	0	0
T21	0	3	0	0
T33	876209	56	0	0
T35	0	1035	0	0
T38	0	889	0	0
T60	0	57	0	0
T61	0	28	0	0
T62	0	25	0	0
T63	0	81	0	0
T64	0	109	0	0
T65	212383	0	0	0
T66	347168	0	0	0
T67	725901	0	0	0
T68	192494	0	0	0
T69	616721	0	0	0
T70	129281	0	0	0
T71	124329	0	0	0
T72	495262	0	0	0