Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.36 98.73 100.00 100.00 100.00 100.00


Total test records in report: 574
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T99 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1947172841 Jul 02 09:04:59 AM PDT 24 Jul 02 09:05:02 AM PDT 24 278085211 ps
T509 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.596995691 Jul 02 09:04:57 AM PDT 24 Jul 02 09:04:59 AM PDT 24 38804862 ps
T510 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1562762585 Jul 02 09:05:10 AM PDT 24 Jul 02 09:05:15 AM PDT 24 4497192912 ps
T511 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.571043111 Jul 02 09:05:09 AM PDT 24 Jul 02 09:05:11 AM PDT 24 199445749 ps
T512 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4179633723 Jul 02 09:05:10 AM PDT 24 Jul 02 09:05:13 AM PDT 24 184597695 ps
T513 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3891947020 Jul 02 09:04:58 AM PDT 24 Jul 02 09:05:01 AM PDT 24 37687243 ps
T514 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1924375276 Jul 02 09:05:13 AM PDT 24 Jul 02 09:05:15 AM PDT 24 36058964 ps
T515 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2394318988 Jul 02 09:05:15 AM PDT 24 Jul 02 09:05:18 AM PDT 24 145382879 ps
T516 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1947783204 Jul 02 09:05:23 AM PDT 24 Jul 02 09:05:25 AM PDT 24 22545310 ps
T517 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1831508142 Jul 02 09:05:19 AM PDT 24 Jul 02 09:05:21 AM PDT 24 50887941 ps
T518 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3539404395 Jul 02 09:05:16 AM PDT 24 Jul 02 09:05:19 AM PDT 24 299374339 ps
T84 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1854928124 Jul 02 09:05:02 AM PDT 24 Jul 02 09:05:04 AM PDT 24 13789673 ps
T519 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2947683465 Jul 02 09:05:12 AM PDT 24 Jul 02 09:05:14 AM PDT 24 146506334 ps
T85 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2085732533 Jul 02 09:04:56 AM PDT 24 Jul 02 09:04:58 AM PDT 24 121357330 ps
T86 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3664345336 Jul 02 09:04:54 AM PDT 24 Jul 02 09:04:56 AM PDT 24 28118960 ps
T520 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1806352204 Jul 02 09:05:15 AM PDT 24 Jul 02 09:05:18 AM PDT 24 407843129 ps
T521 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1675196615 Jul 02 09:05:13 AM PDT 24 Jul 02 09:05:15 AM PDT 24 23782142 ps
T522 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.784867012 Jul 02 09:04:51 AM PDT 24 Jul 02 09:04:55 AM PDT 24 87237397 ps
T523 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1508155836 Jul 02 09:05:04 AM PDT 24 Jul 02 09:05:08 AM PDT 24 146123339 ps
T524 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2864629601 Jul 02 09:05:16 AM PDT 24 Jul 02 09:05:18 AM PDT 24 53417375 ps
T525 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3222745919 Jul 02 09:05:25 AM PDT 24 Jul 02 09:05:27 AM PDT 24 75225500 ps
T526 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1116120014 Jul 02 09:05:21 AM PDT 24 Jul 02 09:05:23 AM PDT 24 16265754 ps
T527 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1394687629 Jul 02 09:05:13 AM PDT 24 Jul 02 09:05:15 AM PDT 24 61364307 ps
T528 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3809977988 Jul 02 09:05:14 AM PDT 24 Jul 02 09:05:17 AM PDT 24 26845362 ps
T529 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3321142559 Jul 02 09:05:15 AM PDT 24 Jul 02 09:05:18 AM PDT 24 14259742 ps
T87 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3490879759 Jul 02 09:05:01 AM PDT 24 Jul 02 09:05:05 AM PDT 24 124021829 ps
T530 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3221416103 Jul 02 09:05:09 AM PDT 24 Jul 02 09:05:11 AM PDT 24 96054485 ps
T88 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.900651278 Jul 02 09:05:13 AM PDT 24 Jul 02 09:05:16 AM PDT 24 14314128 ps
T89 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.617338679 Jul 02 09:04:53 AM PDT 24 Jul 02 09:04:54 AM PDT 24 15229909 ps
T531 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2588254560 Jul 02 09:05:10 AM PDT 24 Jul 02 09:05:15 AM PDT 24 156481215 ps
T532 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3385686202 Jul 02 09:05:12 AM PDT 24 Jul 02 09:05:15 AM PDT 24 92618462 ps
T533 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4199610863 Jul 02 09:05:18 AM PDT 24 Jul 02 09:05:20 AM PDT 24 20530713 ps
T534 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1469633387 Jul 02 09:05:15 AM PDT 24 Jul 02 09:05:18 AM PDT 24 118459671 ps
T535 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2808661641 Jul 02 09:05:22 AM PDT 24 Jul 02 09:05:23 AM PDT 24 24082208 ps
T536 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1645790622 Jul 02 09:05:14 AM PDT 24 Jul 02 09:05:18 AM PDT 24 532555372 ps
T537 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.48157307 Jul 02 09:05:08 AM PDT 24 Jul 02 09:05:10 AM PDT 24 39111584 ps
T538 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.894062572 Jul 02 09:05:00 AM PDT 24 Jul 02 09:05:02 AM PDT 24 17568193 ps
T539 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1359174942 Jul 02 09:05:08 AM PDT 24 Jul 02 09:05:09 AM PDT 24 11760684 ps
T540 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2270355133 Jul 02 09:05:12 AM PDT 24 Jul 02 09:05:15 AM PDT 24 12824824 ps
T541 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2943335362 Jul 02 09:05:10 AM PDT 24 Jul 02 09:05:12 AM PDT 24 21142440 ps
T542 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3458600881 Jul 02 09:05:14 AM PDT 24 Jul 02 09:05:18 AM PDT 24 99619931 ps
T543 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3392634778 Jul 02 09:05:01 AM PDT 24 Jul 02 09:05:05 AM PDT 24 23989263 ps
T544 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3486233254 Jul 02 09:05:03 AM PDT 24 Jul 02 09:05:06 AM PDT 24 138403013 ps
T545 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1724119990 Jul 02 09:05:12 AM PDT 24 Jul 02 09:05:16 AM PDT 24 77945406 ps
T546 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3306690088 Jul 02 09:05:17 AM PDT 24 Jul 02 09:05:19 AM PDT 24 21154724 ps
T547 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3187584762 Jul 02 09:05:08 AM PDT 24 Jul 02 09:05:11 AM PDT 24 214958521 ps
T548 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2905520791 Jul 02 09:05:20 AM PDT 24 Jul 02 09:05:21 AM PDT 24 134442734 ps
T549 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2368749463 Jul 02 09:05:18 AM PDT 24 Jul 02 09:05:20 AM PDT 24 29120391 ps
T550 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3947138571 Jul 02 09:04:57 AM PDT 24 Jul 02 09:04:59 AM PDT 24 322903039 ps
T551 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3621451850 Jul 02 09:05:10 AM PDT 24 Jul 02 09:05:14 AM PDT 24 1548786539 ps
T552 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1025639836 Jul 02 09:04:55 AM PDT 24 Jul 02 09:04:56 AM PDT 24 14095480 ps
T553 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1052340799 Jul 02 09:05:16 AM PDT 24 Jul 02 09:05:19 AM PDT 24 266820045 ps
T554 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3068844194 Jul 02 09:05:00 AM PDT 24 Jul 02 09:05:03 AM PDT 24 19739031 ps
T555 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1590690563 Jul 02 09:05:16 AM PDT 24 Jul 02 09:05:19 AM PDT 24 49789998 ps
T556 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1365328270 Jul 02 09:05:09 AM PDT 24 Jul 02 09:05:12 AM PDT 24 130745393 ps
T557 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.388031942 Jul 02 09:05:04 AM PDT 24 Jul 02 09:05:08 AM PDT 24 52937213 ps
T558 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1836730698 Jul 02 09:05:01 AM PDT 24 Jul 02 09:05:06 AM PDT 24 330400005 ps
T559 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2279816138 Jul 02 09:05:15 AM PDT 24 Jul 02 09:05:18 AM PDT 24 140421221 ps
T560 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2947555083 Jul 02 09:05:12 AM PDT 24 Jul 02 09:05:15 AM PDT 24 35854984 ps
T561 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3175198780 Jul 02 09:05:10 AM PDT 24 Jul 02 09:05:13 AM PDT 24 42135804 ps
T562 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4072311763 Jul 02 09:05:06 AM PDT 24 Jul 02 09:05:08 AM PDT 24 35004878 ps
T563 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1587244300 Jul 02 09:05:17 AM PDT 24 Jul 02 09:05:19 AM PDT 24 10730170 ps
T564 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2884802552 Jul 02 09:05:11 AM PDT 24 Jul 02 09:05:14 AM PDT 24 17131393 ps
T565 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4286138076 Jul 02 09:05:07 AM PDT 24 Jul 02 09:05:09 AM PDT 24 84708669 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.781033839 Jul 02 09:05:01 AM PDT 24 Jul 02 09:05:04 AM PDT 24 44251489 ps
T567 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1582895927 Jul 02 09:05:08 AM PDT 24 Jul 02 09:05:10 AM PDT 24 17567571 ps
T568 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.411104402 Jul 02 09:05:22 AM PDT 24 Jul 02 09:05:24 AM PDT 24 54064834 ps
T569 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1900272263 Jul 02 09:05:07 AM PDT 24 Jul 02 09:05:08 AM PDT 24 240365227 ps
T570 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.812935350 Jul 02 09:05:12 AM PDT 24 Jul 02 09:05:15 AM PDT 24 252117162 ps
T571 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4006989155 Jul 02 09:05:10 AM PDT 24 Jul 02 09:05:14 AM PDT 24 98430126 ps
T572 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.390670434 Jul 02 09:05:18 AM PDT 24 Jul 02 09:05:20 AM PDT 24 15499106 ps
T90 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1618303259 Jul 02 09:05:15 AM PDT 24 Jul 02 09:05:18 AM PDT 24 37964321 ps
T573 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.247651456 Jul 02 09:05:16 AM PDT 24 Jul 02 09:05:19 AM PDT 24 71261102 ps
T574 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3274428909 Jul 02 09:05:12 AM PDT 24 Jul 02 09:05:14 AM PDT 24 30312125 ps

Test location /workspace/coverage/default/48.rv_timer_stress_all.1846143966
Short name T9
Test name
Test status
Simulation time 1735808309703 ps
CPU time 882.91 seconds
Started Jul 02 09:29:06 AM PDT 24
Finished Jul 02 09:43:49 AM PDT 24
Peak memory 191336 kb
Host smart-25801d56-b3e7-4f8b-b95a-0c9a27b34a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846143966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1846143966
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.1084752849
Short name T37
Test name
Test status
Simulation time 88626728823 ps
CPU time 618.37 seconds
Started Jul 02 09:28:31 AM PDT 24
Finished Jul 02 09:38:51 AM PDT 24
Peak memory 207108 kb
Host smart-68893fb1-b9b6-4ad7-8e45-4ff648d8ceae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084752849 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.1084752849
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.4005555928
Short name T40
Test name
Test status
Simulation time 1008011793455 ps
CPU time 5046.04 seconds
Started Jul 02 09:28:27 AM PDT 24
Finished Jul 02 10:52:35 AM PDT 24
Peak memory 191364 kb
Host smart-fa60e34f-4503-4188-bb47-71a789613f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005555928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.4005555928
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1991581589
Short name T28
Test name
Test status
Simulation time 52422022 ps
CPU time 0.81 seconds
Started Jul 02 09:05:13 AM PDT 24
Finished Jul 02 09:05:16 AM PDT 24
Peak memory 193176 kb
Host smart-4dcbe882-0f81-4daf-a9f0-d96ba3602cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991581589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1991581589
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1404741088
Short name T131
Test name
Test status
Simulation time 3216423310419 ps
CPU time 2075.6 seconds
Started Jul 02 09:28:36 AM PDT 24
Finished Jul 02 10:03:13 AM PDT 24
Peak memory 191308 kb
Host smart-f74791af-282d-461c-9700-308c65191811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404741088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1404741088
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1096394385
Short name T100
Test name
Test status
Simulation time 1473975427279 ps
CPU time 1823.31 seconds
Started Jul 02 09:28:27 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 196088 kb
Host smart-73526ba3-7b53-4043-a7a0-f72e0c765660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096394385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1096394385
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3139783415
Short name T110
Test name
Test status
Simulation time 2736504468606 ps
CPU time 1647.31 seconds
Started Jul 02 09:28:20 AM PDT 24
Finished Jul 02 09:55:48 AM PDT 24
Peak memory 191372 kb
Host smart-06943ec6-cba6-472a-b6d7-cf8648c8cce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139783415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3139783415
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2085401262
Short name T152
Test name
Test status
Simulation time 1625254445099 ps
CPU time 1844.82 seconds
Started Jul 02 09:28:27 AM PDT 24
Finished Jul 02 09:59:14 AM PDT 24
Peak memory 191312 kb
Host smart-7921ee47-11d3-4d7b-ae8a-7d25f0668ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085401262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2085401262
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1617806193
Short name T287
Test name
Test status
Simulation time 541089557180 ps
CPU time 1115.32 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:46:38 AM PDT 24
Peak memory 191276 kb
Host smart-5fc5eb87-6203-4cfd-b918-8b7b8db7c091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617806193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1617806193
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3642071197
Short name T74
Test name
Test status
Simulation time 105746506 ps
CPU time 0.7 seconds
Started Jul 02 09:05:01 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 182288 kb
Host smart-ffc8cc11-cdca-4cc3-8e54-578ee8a4abaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642071197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3642071197
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2098434598
Short name T188
Test name
Test status
Simulation time 6434160677959 ps
CPU time 4934.68 seconds
Started Jul 02 09:28:14 AM PDT 24
Finished Jul 02 10:50:30 AM PDT 24
Peak memory 191344 kb
Host smart-f70788a2-a147-497a-b28d-84eda9d39bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098434598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2098434598
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1507042840
Short name T267
Test name
Test status
Simulation time 407147302678 ps
CPU time 3928.96 seconds
Started Jul 02 09:28:17 AM PDT 24
Finished Jul 02 10:33:48 AM PDT 24
Peak memory 191304 kb
Host smart-8904bda5-3d4b-4bd1-a5bd-0e125da4f877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507042840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1507042840
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3549914079
Short name T3
Test name
Test status
Simulation time 616319497502 ps
CPU time 1280.43 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:50:05 AM PDT 24
Peak memory 191360 kb
Host smart-ef868319-e8a5-4377-859d-39228141a72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549914079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3549914079
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3909387689
Short name T63
Test name
Test status
Simulation time 2307853536045 ps
CPU time 1919.68 seconds
Started Jul 02 09:28:31 AM PDT 24
Finished Jul 02 10:00:32 AM PDT 24
Peak memory 195296 kb
Host smart-b65835de-3af8-4d73-898c-ea85225fb651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909387689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3909387689
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2538654383
Short name T18
Test name
Test status
Simulation time 322725346 ps
CPU time 0.92 seconds
Started Jul 02 09:28:00 AM PDT 24
Finished Jul 02 09:28:02 AM PDT 24
Peak memory 213532 kb
Host smart-247612f1-a694-4993-803c-c294564ca8fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538654383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2538654383
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1464992661
Short name T191
Test name
Test status
Simulation time 723134650919 ps
CPU time 898.39 seconds
Started Jul 02 09:28:17 AM PDT 24
Finished Jul 02 09:43:17 AM PDT 24
Peak memory 191364 kb
Host smart-0257bd6c-0c92-42c3-849a-a1fc1e570251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464992661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1464992661
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3026059003
Short name T184
Test name
Test status
Simulation time 3322399415020 ps
CPU time 3873.26 seconds
Started Jul 02 09:29:08 AM PDT 24
Finished Jul 02 10:33:42 AM PDT 24
Peak memory 191356 kb
Host smart-902d9ef6-32af-45aa-9507-1fe2c4c8b779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026059003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3026059003
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.402701944
Short name T273
Test name
Test status
Simulation time 1022535372606 ps
CPU time 3206.58 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 10:21:55 AM PDT 24
Peak memory 191364 kb
Host smart-c6e48fa1-85e7-4ffc-b716-c726dd4f7975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402701944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
402701944
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/109.rv_timer_random.1751665331
Short name T142
Test name
Test status
Simulation time 137102660874 ps
CPU time 260.25 seconds
Started Jul 02 09:29:50 AM PDT 24
Finished Jul 02 09:34:11 AM PDT 24
Peak memory 191328 kb
Host smart-2151294d-6670-45cd-a828-51fdff2edde9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751665331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1751665331
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.2348537006
Short name T150
Test name
Test status
Simulation time 830251319688 ps
CPU time 632.53 seconds
Started Jul 02 09:28:23 AM PDT 24
Finished Jul 02 09:38:56 AM PDT 24
Peak memory 191316 kb
Host smart-37898e21-8bbe-470d-956f-63efdcc43b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348537006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2348537006
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1822749769
Short name T241
Test name
Test status
Simulation time 151221263558 ps
CPU time 370.64 seconds
Started Jul 02 09:29:17 AM PDT 24
Finished Jul 02 09:35:28 AM PDT 24
Peak memory 191316 kb
Host smart-2050f3e7-2ebf-41bc-bfe7-c96475124037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822749769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1822749769
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3832919879
Short name T252
Test name
Test status
Simulation time 190841455377 ps
CPU time 621.99 seconds
Started Jul 02 09:30:25 AM PDT 24
Finished Jul 02 09:40:48 AM PDT 24
Peak memory 191364 kb
Host smart-cb5e645a-9d4a-42f4-9dae-500dc1c3d7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832919879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3832919879
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.2384515079
Short name T269
Test name
Test status
Simulation time 688416650857 ps
CPU time 481.53 seconds
Started Jul 02 09:28:21 AM PDT 24
Finished Jul 02 09:36:23 AM PDT 24
Peak memory 191320 kb
Host smart-8bd834e3-2d56-4141-9d0b-f33efaf08d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384515079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2384515079
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2806814572
Short name T171
Test name
Test status
Simulation time 341356667038 ps
CPU time 1064.21 seconds
Started Jul 02 09:27:57 AM PDT 24
Finished Jul 02 09:45:41 AM PDT 24
Peak memory 195748 kb
Host smart-e29030d6-1ac7-47f8-b051-31f1e5cadd15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806814572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2806814572
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/126.rv_timer_random.3628714288
Short name T265
Test name
Test status
Simulation time 1728729193187 ps
CPU time 411.1 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 09:36:49 AM PDT 24
Peak memory 191348 kb
Host smart-630c8462-2e10-4a85-80d8-3fa826f56be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628714288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3628714288
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2343293418
Short name T130
Test name
Test status
Simulation time 362557918122 ps
CPU time 1192.12 seconds
Started Jul 02 09:30:35 AM PDT 24
Finished Jul 02 09:50:28 AM PDT 24
Peak memory 191316 kb
Host smart-0090f877-d106-40ec-928b-91cdbd6966b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343293418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2343293418
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.2171265538
Short name T134
Test name
Test status
Simulation time 620606149896 ps
CPU time 762.46 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:40:44 AM PDT 24
Peak memory 194620 kb
Host smart-8a1c0771-4125-4f70-85fe-c206512d70cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171265538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2171265538
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1368156971
Short name T7
Test name
Test status
Simulation time 159821453711 ps
CPU time 313.03 seconds
Started Jul 02 09:30:17 AM PDT 24
Finished Jul 02 09:35:30 AM PDT 24
Peak memory 191364 kb
Host smart-3192cf6c-a31c-41b1-905e-a41151d01954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368156971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1368156971
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3641452786
Short name T202
Test name
Test status
Simulation time 415213682544 ps
CPU time 1884.2 seconds
Started Jul 02 09:30:19 AM PDT 24
Finished Jul 02 10:01:43 AM PDT 24
Peak memory 191328 kb
Host smart-a8cbd13e-8697-4861-ab09-0c8d29195771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641452786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3641452786
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.3605224177
Short name T149
Test name
Test status
Simulation time 199199425266 ps
CPU time 294.29 seconds
Started Jul 02 09:28:59 AM PDT 24
Finished Jul 02 09:33:54 AM PDT 24
Peak memory 191372 kb
Host smart-cb7f8a0f-17de-489d-b53f-108a08e1b2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605224177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3605224177
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.195130364
Short name T44
Test name
Test status
Simulation time 186929845973 ps
CPU time 318.58 seconds
Started Jul 02 09:28:06 AM PDT 24
Finished Jul 02 09:33:25 AM PDT 24
Peak memory 192568 kb
Host smart-86786894-c87e-41ae-bcf2-c06444d9c4d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195130364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.195130364
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3135755097
Short name T235
Test name
Test status
Simulation time 1513183904952 ps
CPU time 405.08 seconds
Started Jul 02 09:28:08 AM PDT 24
Finished Jul 02 09:34:54 AM PDT 24
Peak memory 183140 kb
Host smart-406be204-8738-4711-a8d6-c996a29faa54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135755097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3135755097
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/172.rv_timer_random.1138231199
Short name T126
Test name
Test status
Simulation time 1107804664620 ps
CPU time 486.38 seconds
Started Jul 02 09:30:20 AM PDT 24
Finished Jul 02 09:38:26 AM PDT 24
Peak memory 191348 kb
Host smart-ef52f445-58c8-457d-af2e-931df9d09daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138231199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1138231199
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2041346103
Short name T326
Test name
Test status
Simulation time 300542092371 ps
CPU time 490.98 seconds
Started Jul 02 09:28:19 AM PDT 24
Finished Jul 02 09:36:30 AM PDT 24
Peak memory 183156 kb
Host smart-92135949-a24c-42e8-8b13-e38d9d35971f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041346103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2041346103
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.991699510
Short name T161
Test name
Test status
Simulation time 244075180557 ps
CPU time 387.8 seconds
Started Jul 02 09:28:17 AM PDT 24
Finished Jul 02 09:34:46 AM PDT 24
Peak memory 183168 kb
Host smart-20d81c4e-10dd-4f60-87e4-7909694eb21f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991699510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.991699510
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1488902510
Short name T207
Test name
Test status
Simulation time 197983929754 ps
CPU time 195.52 seconds
Started Jul 02 09:28:25 AM PDT 24
Finished Jul 02 09:31:41 AM PDT 24
Peak memory 183104 kb
Host smart-26b7cc2d-aa81-4a03-9987-849e53fa582c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488902510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1488902510
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.2633120247
Short name T221
Test name
Test status
Simulation time 517965223647 ps
CPU time 294.6 seconds
Started Jul 02 09:28:29 AM PDT 24
Finished Jul 02 09:33:25 AM PDT 24
Peak memory 191344 kb
Host smart-d3356fef-9277-4723-9a95-eedf5c66a13b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633120247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2633120247
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.3621256078
Short name T101
Test name
Test status
Simulation time 475961295570 ps
CPU time 706.91 seconds
Started Jul 02 09:28:04 AM PDT 24
Finished Jul 02 09:39:52 AM PDT 24
Peak memory 191316 kb
Host smart-c6190e9d-0b47-4d6c-8cc9-8a283cdaca76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621256078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3621256078
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.511384603
Short name T293
Test name
Test status
Simulation time 600401308630 ps
CPU time 740.35 seconds
Started Jul 02 09:29:33 AM PDT 24
Finished Jul 02 09:41:54 AM PDT 24
Peak memory 191368 kb
Host smart-4b450cc8-1e2f-4926-b999-9989ae799351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511384603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.511384603
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1910585332
Short name T210
Test name
Test status
Simulation time 63128154730 ps
CPU time 101.48 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:29:40 AM PDT 24
Peak memory 183164 kb
Host smart-0600178a-4a41-4fbc-8a74-aef4cec0889b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910585332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1910585332
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.1736662697
Short name T107
Test name
Test status
Simulation time 188834201163 ps
CPU time 270.78 seconds
Started Jul 02 09:29:37 AM PDT 24
Finished Jul 02 09:34:08 AM PDT 24
Peak memory 191376 kb
Host smart-283aac64-8967-4c01-a898-a8c7bb0c43f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736662697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1736662697
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.214589555
Short name T284
Test name
Test status
Simulation time 270191147233 ps
CPU time 317.11 seconds
Started Jul 02 09:29:55 AM PDT 24
Finished Jul 02 09:35:13 AM PDT 24
Peak memory 191364 kb
Host smart-cf2d6ec7-74c2-48ad-9e92-afa92aed360b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214589555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.214589555
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3152900414
Short name T450
Test name
Test status
Simulation time 164885206166 ps
CPU time 748.82 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 09:42:28 AM PDT 24
Peak memory 191356 kb
Host smart-69b74cdc-e4c6-4d3c-b283-d618513106bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152900414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3152900414
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2340875652
Short name T33
Test name
Test status
Simulation time 2682003561598 ps
CPU time 3495.83 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 10:26:44 AM PDT 24
Peak memory 191352 kb
Host smart-3fe20281-e6d8-4823-860b-0d929aa42b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340875652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2340875652
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3817348757
Short name T251
Test name
Test status
Simulation time 558359382107 ps
CPU time 951.64 seconds
Started Jul 02 09:28:28 AM PDT 24
Finished Jul 02 09:44:21 AM PDT 24
Peak memory 191320 kb
Host smart-720d738a-0ff1-48d2-a738-bbab4f95b84c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817348757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3817348757
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2436502477
Short name T209
Test name
Test status
Simulation time 166568427886 ps
CPU time 703.1 seconds
Started Jul 02 09:28:44 AM PDT 24
Finished Jul 02 09:40:28 AM PDT 24
Peak memory 191336 kb
Host smart-03584589-a540-4a46-8d6f-1ea50f0cd838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436502477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2436502477
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.631564714
Short name T286
Test name
Test status
Simulation time 261632500772 ps
CPU time 435.79 seconds
Started Jul 02 09:28:58 AM PDT 24
Finished Jul 02 09:36:14 AM PDT 24
Peak memory 191320 kb
Host smart-c5d40db9-2a93-445b-83a6-7b4cf8b4273e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631564714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
631564714
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1431002667
Short name T61
Test name
Test status
Simulation time 908162714319 ps
CPU time 752.7 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:40:36 AM PDT 24
Peak memory 191308 kb
Host smart-c4fc07ee-4ad0-4e10-b06b-108462b9bfb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431002667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1431002667
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2268995108
Short name T30
Test name
Test status
Simulation time 159776464 ps
CPU time 1.3 seconds
Started Jul 02 09:04:55 AM PDT 24
Finished Jul 02 09:04:57 AM PDT 24
Peak memory 182816 kb
Host smart-9c0edd23-7c3a-4b14-8d44-a9d27e9573d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268995108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2268995108
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.784821041
Short name T42
Test name
Test status
Simulation time 764801989916 ps
CPU time 758.85 seconds
Started Jul 02 09:28:12 AM PDT 24
Finished Jul 02 09:40:52 AM PDT 24
Peak memory 183176 kb
Host smart-0843f497-05a6-408b-9143-12fd5ab1a7b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784821041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.784821041
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/175.rv_timer_random.2137135418
Short name T223
Test name
Test status
Simulation time 36169692066 ps
CPU time 50.84 seconds
Started Jul 02 09:30:24 AM PDT 24
Finished Jul 02 09:31:15 AM PDT 24
Peak memory 191360 kb
Host smart-cd417c55-d103-4c2d-b26a-3667b3b4c433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137135418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2137135418
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.1904406251
Short name T239
Test name
Test status
Simulation time 232321198201 ps
CPU time 243.55 seconds
Started Jul 02 09:28:16 AM PDT 24
Finished Jul 02 09:32:20 AM PDT 24
Peak memory 191360 kb
Host smart-bc0387d8-4807-4e53-a996-39ecc5cb3540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904406251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1904406251
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1524270046
Short name T177
Test name
Test status
Simulation time 270485677485 ps
CPU time 442.24 seconds
Started Jul 02 09:28:23 AM PDT 24
Finished Jul 02 09:35:46 AM PDT 24
Peak memory 183160 kb
Host smart-2757792c-57e6-4aa7-a6da-89f50f98ca80
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524270046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1524270046
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3251295740
Short name T43
Test name
Test status
Simulation time 361804982621 ps
CPU time 911.93 seconds
Started Jul 02 09:29:00 AM PDT 24
Finished Jul 02 09:44:12 AM PDT 24
Peak memory 195556 kb
Host smart-77c13a0b-675c-4e47-b14d-a298c411cdb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251295740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3251295740
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/58.rv_timer_random.349770289
Short name T108
Test name
Test status
Simulation time 193288240479 ps
CPU time 1570.59 seconds
Started Jul 02 09:29:17 AM PDT 24
Finished Jul 02 09:55:28 AM PDT 24
Peak memory 191352 kb
Host smart-d1bccb1d-ea60-4284-900f-cf66300ff7d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349770289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.349770289
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2758245561
Short name T160
Test name
Test status
Simulation time 167498073462 ps
CPU time 559.26 seconds
Started Jul 02 09:29:29 AM PDT 24
Finished Jul 02 09:38:49 AM PDT 24
Peak memory 191372 kb
Host smart-e828c6b9-d3c3-4173-9781-dd44082ec66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758245561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2758245561
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.240396867
Short name T192
Test name
Test status
Simulation time 576089394164 ps
CPU time 280.38 seconds
Started Jul 02 09:29:30 AM PDT 24
Finished Jul 02 09:34:11 AM PDT 24
Peak memory 193608 kb
Host smart-f16c30b5-dd51-47e7-8bd5-864fbba15158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240396867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.240396867
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2227083230
Short name T124
Test name
Test status
Simulation time 137219906517 ps
CPU time 745.05 seconds
Started Jul 02 09:29:31 AM PDT 24
Finished Jul 02 09:41:56 AM PDT 24
Peak memory 191316 kb
Host smart-24bc79e1-1398-4a91-b71f-fd332da9492d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227083230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2227083230
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1266640837
Short name T197
Test name
Test status
Simulation time 249517624894 ps
CPU time 387.36 seconds
Started Jul 02 09:28:05 AM PDT 24
Finished Jul 02 09:34:33 AM PDT 24
Peak memory 191356 kb
Host smart-f8c1442f-3b1d-4456-b28f-4bd0717317d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266640837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1266640837
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.349939827
Short name T93
Test name
Test status
Simulation time 61074176 ps
CPU time 0.79 seconds
Started Jul 02 09:04:55 AM PDT 24
Finished Jul 02 09:04:57 AM PDT 24
Peak memory 191260 kb
Host smart-41500be7-725d-4cf8-8ecc-2fadb373098f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349939827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.349939827
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_random.3964420726
Short name T303
Test name
Test status
Simulation time 58937331144 ps
CPU time 311.03 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:33:10 AM PDT 24
Peak memory 191344 kb
Host smart-4dee8cda-0be9-4625-ae4f-4c7d722c506e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964420726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3964420726
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2038639543
Short name T111
Test name
Test status
Simulation time 111432062570 ps
CPU time 505.09 seconds
Started Jul 02 09:29:53 AM PDT 24
Finished Jul 02 09:38:19 AM PDT 24
Peak memory 191360 kb
Host smart-a35ef5ec-2e16-45bb-99db-4da111e3464e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038639543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2038639543
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1609476213
Short name T155
Test name
Test status
Simulation time 518508484050 ps
CPU time 2011.56 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 10:03:30 AM PDT 24
Peak memory 191312 kb
Host smart-a3a649d6-3cf1-4134-81e1-2ed8d9b5c897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609476213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1609476213
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2413767689
Short name T243
Test name
Test status
Simulation time 840037544603 ps
CPU time 236.72 seconds
Started Jul 02 09:30:06 AM PDT 24
Finished Jul 02 09:34:03 AM PDT 24
Peak memory 194892 kb
Host smart-f9a298eb-0be2-493b-9a1f-100951982c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413767689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2413767689
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.3088603273
Short name T282
Test name
Test status
Simulation time 535723962938 ps
CPU time 468.6 seconds
Started Jul 02 09:30:20 AM PDT 24
Finished Jul 02 09:38:09 AM PDT 24
Peak memory 191324 kb
Host smart-25bef576-b67b-4f8d-a42f-ba1dfb0368b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088603273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3088603273
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3833577253
Short name T337
Test name
Test status
Simulation time 123770528110 ps
CPU time 447.92 seconds
Started Jul 02 09:28:28 AM PDT 24
Finished Jul 02 09:35:57 AM PDT 24
Peak memory 191328 kb
Host smart-3e173827-3d2e-45ca-aa5d-1f6c64db2a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833577253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3833577253
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random.2293422399
Short name T119
Test name
Test status
Simulation time 130984062800 ps
CPU time 201.14 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:31:23 AM PDT 24
Peak memory 191336 kb
Host smart-d8bd8a2e-814b-414b-b29a-f8ac448e9e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293422399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2293422399
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1915921376
Short name T314
Test name
Test status
Simulation time 45937272562 ps
CPU time 65.34 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:29:09 AM PDT 24
Peak memory 183180 kb
Host smart-9f47af66-5191-4d58-a853-f9a94927c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915921376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1915921376
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.876244230
Short name T68
Test name
Test status
Simulation time 519278377135 ps
CPU time 427.67 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:35:11 AM PDT 24
Peak memory 193448 kb
Host smart-3c6908a0-d626-4f28-a7c0-07383616ff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876244230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.876244230
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/94.rv_timer_random.3835803314
Short name T214
Test name
Test status
Simulation time 183719306220 ps
CPU time 426.33 seconds
Started Jul 02 09:29:32 AM PDT 24
Finished Jul 02 09:36:39 AM PDT 24
Peak memory 191308 kb
Host smart-406516ec-4031-4ab0-99a3-186699782c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835803314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3835803314
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3910298127
Short name T245
Test name
Test status
Simulation time 137047790372 ps
CPU time 367.23 seconds
Started Jul 02 09:29:44 AM PDT 24
Finished Jul 02 09:35:51 AM PDT 24
Peak memory 191340 kb
Host smart-0e4e778b-173c-4c45-8221-f3289a3c6456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910298127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3910298127
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1405252378
Short name T228
Test name
Test status
Simulation time 600545005459 ps
CPU time 288.62 seconds
Started Jul 02 09:29:44 AM PDT 24
Finished Jul 02 09:34:33 AM PDT 24
Peak memory 191368 kb
Host smart-bb725268-9ba6-4681-8507-f477ce54408a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405252378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1405252378
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.175380975
Short name T346
Test name
Test status
Simulation time 126818802079 ps
CPU time 195.14 seconds
Started Jul 02 09:28:09 AM PDT 24
Finished Jul 02 09:31:25 AM PDT 24
Peak memory 183340 kb
Host smart-1c6377c6-9398-4ac1-8e54-a29797245fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175380975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
175380975
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.3381421523
Short name T193
Test name
Test status
Simulation time 166622114970 ps
CPU time 199.56 seconds
Started Jul 02 09:29:48 AM PDT 24
Finished Jul 02 09:33:08 AM PDT 24
Peak memory 191372 kb
Host smart-59e8232f-ab33-4531-9d30-417343ae160b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381421523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3381421523
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.502609279
Short name T10
Test name
Test status
Simulation time 97795425980 ps
CPU time 74.96 seconds
Started Jul 02 09:29:47 AM PDT 24
Finished Jul 02 09:31:02 AM PDT 24
Peak memory 183172 kb
Host smart-4d850617-b365-4489-be26-57d864eb35b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502609279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.502609279
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4036890317
Short name T306
Test name
Test status
Simulation time 316276647758 ps
CPU time 289.83 seconds
Started Jul 02 09:29:49 AM PDT 24
Finished Jul 02 09:34:39 AM PDT 24
Peak memory 191312 kb
Host smart-6dd42d14-0e0f-4553-8af9-14f529b4f9c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036890317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4036890317
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1394032069
Short name T325
Test name
Test status
Simulation time 115159290487 ps
CPU time 1866.47 seconds
Started Jul 02 09:28:10 AM PDT 24
Finished Jul 02 09:59:17 AM PDT 24
Peak memory 191332 kb
Host smart-a528a605-780a-4e38-bb2c-7c0d06962949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394032069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1394032069
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/128.rv_timer_random.1000283943
Short name T148
Test name
Test status
Simulation time 302980410222 ps
CPU time 281.92 seconds
Started Jul 02 09:29:54 AM PDT 24
Finished Jul 02 09:34:37 AM PDT 24
Peak memory 191332 kb
Host smart-9525dd8f-c002-4541-99c9-4605927d15ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000283943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1000283943
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2878893559
Short name T298
Test name
Test status
Simulation time 130865220549 ps
CPU time 487.08 seconds
Started Jul 02 09:29:54 AM PDT 24
Finished Jul 02 09:38:02 AM PDT 24
Peak memory 191304 kb
Host smart-c16328a9-b5ee-4329-9a1f-2847108a9b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878893559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2878893559
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3775664696
Short name T203
Test name
Test status
Simulation time 775746278236 ps
CPU time 265.99 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 09:34:24 AM PDT 24
Peak memory 191324 kb
Host smart-4de58e3a-b1f7-4a12-aac8-a4279f483a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775664696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3775664696
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1902666060
Short name T128
Test name
Test status
Simulation time 129575025291 ps
CPU time 242.6 seconds
Started Jul 02 09:30:02 AM PDT 24
Finished Jul 02 09:34:05 AM PDT 24
Peak memory 193848 kb
Host smart-60725761-bb46-498d-8dfc-1e70287cd7ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902666060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1902666060
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3560922312
Short name T125
Test name
Test status
Simulation time 11755273704 ps
CPU time 10.5 seconds
Started Jul 02 09:30:14 AM PDT 24
Finished Jul 02 09:30:25 AM PDT 24
Peak memory 183128 kb
Host smart-709bb6a6-72ba-41c2-9420-3d32b96269e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560922312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3560922312
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3574374286
Short name T294
Test name
Test status
Simulation time 399147582943 ps
CPU time 561.53 seconds
Started Jul 02 09:30:15 AM PDT 24
Finished Jul 02 09:39:36 AM PDT 24
Peak memory 191312 kb
Host smart-6f1f592e-fa00-4ed2-8d9f-4a8e55879a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574374286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3574374286
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.660026498
Short name T264
Test name
Test status
Simulation time 297274152505 ps
CPU time 306.35 seconds
Started Jul 02 09:30:15 AM PDT 24
Finished Jul 02 09:35:22 AM PDT 24
Peak memory 191368 kb
Host smart-386fda4a-b3f4-4d8b-87be-1cac46e5b7cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660026498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.660026498
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2961847528
Short name T344
Test name
Test status
Simulation time 72260890729 ps
CPU time 260.83 seconds
Started Jul 02 09:30:36 AM PDT 24
Finished Jul 02 09:34:58 AM PDT 24
Peak memory 183140 kb
Host smart-29a10005-8b7b-4ff7-b09e-9cad0810d3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961847528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2961847528
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1126926923
Short name T153
Test name
Test status
Simulation time 348300825024 ps
CPU time 379.54 seconds
Started Jul 02 09:30:39 AM PDT 24
Finished Jul 02 09:36:59 AM PDT 24
Peak memory 191316 kb
Host smart-411d3f49-737f-451e-9355-4ef9191a4ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126926923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1126926923
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.510599647
Short name T138
Test name
Test status
Simulation time 304022262957 ps
CPU time 1640.17 seconds
Started Jul 02 09:28:23 AM PDT 24
Finished Jul 02 09:55:45 AM PDT 24
Peak memory 191340 kb
Host smart-1f1fc471-3356-4909-b4fc-ae2f5d5bef7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510599647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.510599647
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.1418887665
Short name T349
Test name
Test status
Simulation time 275556235306 ps
CPU time 506.57 seconds
Started Jul 02 09:28:27 AM PDT 24
Finished Jul 02 09:36:55 AM PDT 24
Peak memory 191320 kb
Host smart-f8a084f2-d5a8-4a4c-a622-2c166c7e7258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418887665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1418887665
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3224326773
Short name T102
Test name
Test status
Simulation time 6301216625700 ps
CPU time 2089.55 seconds
Started Jul 02 09:28:35 AM PDT 24
Finished Jul 02 10:03:26 AM PDT 24
Peak memory 183132 kb
Host smart-338e20fb-366e-4e42-87b5-e673f343b71e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224326773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3224326773
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random.2789443962
Short name T69
Test name
Test status
Simulation time 150930088552 ps
CPU time 114.86 seconds
Started Jul 02 09:28:56 AM PDT 24
Finished Jul 02 09:30:52 AM PDT 24
Peak memory 183116 kb
Host smart-32082f05-00cd-4e8d-a6a0-1d8be53711a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789443962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2789443962
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.4177624362
Short name T135
Test name
Test status
Simulation time 120022464175 ps
CPU time 132.62 seconds
Started Jul 02 09:29:17 AM PDT 24
Finished Jul 02 09:31:30 AM PDT 24
Peak memory 191332 kb
Host smart-68aebce3-48f6-4070-9277-ad930c1e1b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177624362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.4177624362
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4059068185
Short name T115
Test name
Test status
Simulation time 136715309076 ps
CPU time 1374.93 seconds
Started Jul 02 09:29:28 AM PDT 24
Finished Jul 02 09:52:23 AM PDT 24
Peak memory 191328 kb
Host smart-3f6bc196-6aaf-4e73-ac65-ed3b057cc321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059068185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4059068185
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.617338679
Short name T89
Test name
Test status
Simulation time 15229909 ps
CPU time 0.73 seconds
Started Jul 02 09:04:53 AM PDT 24
Finished Jul 02 09:04:54 AM PDT 24
Peak memory 182312 kb
Host smart-d65fb562-90e2-409e-ab25-3a7b163c56c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617338679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.617338679
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3891947020
Short name T513
Test name
Test status
Simulation time 37687243 ps
CPU time 1.46 seconds
Started Jul 02 09:04:58 AM PDT 24
Finished Jul 02 09:05:01 AM PDT 24
Peak memory 190672 kb
Host smart-579c5733-e3ec-4100-ae2c-ab146c498296
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891947020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3891947020
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1534869977
Short name T468
Test name
Test status
Simulation time 29781128 ps
CPU time 0.62 seconds
Started Jul 02 09:04:53 AM PDT 24
Finished Jul 02 09:04:54 AM PDT 24
Peak memory 191532 kb
Host smart-b796369a-6eea-4689-8b7f-83118b82521a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534869977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1534869977
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3222745919
Short name T525
Test name
Test status
Simulation time 75225500 ps
CPU time 0.97 seconds
Started Jul 02 09:05:25 AM PDT 24
Finished Jul 02 09:05:27 AM PDT 24
Peak memory 196512 kb
Host smart-0f97dde0-9557-4d66-9d69-d275cef3b7f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222745919 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3222745919
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3664345336
Short name T86
Test name
Test status
Simulation time 28118960 ps
CPU time 0.59 seconds
Started Jul 02 09:04:54 AM PDT 24
Finished Jul 02 09:04:56 AM PDT 24
Peak memory 182292 kb
Host smart-d69d0f53-5ffa-40c5-b42f-87d325a3246b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664345336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3664345336
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3571759761
Short name T454
Test name
Test status
Simulation time 39067733 ps
CPU time 0.57 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:03 AM PDT 24
Peak memory 182180 kb
Host smart-9e240b6e-69da-441e-b820-f2fcd5d62522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571759761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3571759761
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1930363647
Short name T39
Test name
Test status
Simulation time 94966799 ps
CPU time 2.15 seconds
Started Jul 02 09:05:07 AM PDT 24
Finished Jul 02 09:05:10 AM PDT 24
Peak memory 197092 kb
Host smart-caf69782-521d-43fc-a8e0-6fb44335f4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930363647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1930363647
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2036494574
Short name T502
Test name
Test status
Simulation time 1069720546 ps
CPU time 2.41 seconds
Started Jul 02 09:04:59 AM PDT 24
Finished Jul 02 09:05:03 AM PDT 24
Peak memory 193388 kb
Host smart-cd1a7e1a-d8db-4b90-9775-b6e5251c42dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036494574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2036494574
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.401118048
Short name T82
Test name
Test status
Simulation time 15196666 ps
CPU time 0.57 seconds
Started Jul 02 09:04:58 AM PDT 24
Finished Jul 02 09:05:00 AM PDT 24
Peak memory 182332 kb
Host smart-bb58e8ad-249d-40fa-bd49-111ae8a97a2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401118048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.401118048
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.74990651
Short name T479
Test name
Test status
Simulation time 23789306 ps
CPU time 0.73 seconds
Started Jul 02 09:05:06 AM PDT 24
Finished Jul 02 09:05:08 AM PDT 24
Peak memory 195080 kb
Host smart-a0fa02a2-74d8-48a6-8020-97f17d69fab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74990651 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.74990651
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2590005712
Short name T72
Test name
Test status
Simulation time 40337652 ps
CPU time 0.52 seconds
Started Jul 02 09:04:55 AM PDT 24
Finished Jul 02 09:04:56 AM PDT 24
Peak memory 182100 kb
Host smart-dbe221b0-188d-4839-8558-91e728735a3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590005712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2590005712
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1025639836
Short name T552
Test name
Test status
Simulation time 14095480 ps
CPU time 0.56 seconds
Started Jul 02 09:04:55 AM PDT 24
Finished Jul 02 09:04:56 AM PDT 24
Peak memory 182192 kb
Host smart-a3557909-6f29-4c52-a02d-775109437d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025639836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1025639836
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.781033839
Short name T566
Test name
Test status
Simulation time 44251489 ps
CPU time 0.61 seconds
Started Jul 02 09:05:01 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 191516 kb
Host smart-5a02cbbf-d79d-4aac-9b24-2ca3bf812385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781033839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.781033839
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.784867012
Short name T522
Test name
Test status
Simulation time 87237397 ps
CPU time 2.24 seconds
Started Jul 02 09:04:51 AM PDT 24
Finished Jul 02 09:04:55 AM PDT 24
Peak memory 197100 kb
Host smart-89a709eb-9037-48f2-9ad6-c9656a54d5df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784867012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.784867012
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1947172841
Short name T99
Test name
Test status
Simulation time 278085211 ps
CPU time 1.27 seconds
Started Jul 02 09:04:59 AM PDT 24
Finished Jul 02 09:05:02 AM PDT 24
Peak memory 195044 kb
Host smart-a2a2b5dd-ae9c-4d3a-99c7-597b8cf2ebbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947172841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1947172841
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3486233254
Short name T544
Test name
Test status
Simulation time 138403013 ps
CPU time 0.92 seconds
Started Jul 02 09:05:03 AM PDT 24
Finished Jul 02 09:05:06 AM PDT 24
Peak memory 196408 kb
Host smart-929f27f4-6a1f-4a54-9685-9cf018772784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486233254 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3486233254
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2270355133
Short name T540
Test name
Test status
Simulation time 12824824 ps
CPU time 0.57 seconds
Started Jul 02 09:05:12 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 182300 kb
Host smart-7ad460d2-00bd-4719-a5cb-b7141184bce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270355133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2270355133
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1632118830
Short name T487
Test name
Test status
Simulation time 18409684 ps
CPU time 0.54 seconds
Started Jul 02 09:05:05 AM PDT 24
Finished Jul 02 09:05:06 AM PDT 24
Peak memory 182188 kb
Host smart-634502d4-f83a-4cac-bc98-4939c267c9bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632118830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1632118830
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3602148159
Short name T91
Test name
Test status
Simulation time 46798262 ps
CPU time 0.7 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 192640 kb
Host smart-2701016a-1eef-4a7f-a6f7-44018493f61c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602148159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3602148159
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1724119990
Short name T545
Test name
Test status
Simulation time 77945406 ps
CPU time 1.91 seconds
Started Jul 02 09:05:12 AM PDT 24
Finished Jul 02 09:05:16 AM PDT 24
Peak memory 197072 kb
Host smart-1e261936-744b-4bd4-800a-9f94ed0af75d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724119990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1724119990
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1373272917
Short name T29
Test name
Test status
Simulation time 38694889 ps
CPU time 0.81 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 193444 kb
Host smart-6bd6f86b-7c74-4a3c-89eb-7055f23c99d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373272917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1373272917
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1342003382
Short name T55
Test name
Test status
Simulation time 101120531 ps
CPU time 0.8 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 195792 kb
Host smart-3afb894e-047b-40ad-b568-5c3dc60f2914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342003382 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1342003382
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2943335362
Short name T541
Test name
Test status
Simulation time 21142440 ps
CPU time 0.53 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:12 AM PDT 24
Peak memory 182272 kb
Host smart-d0a178c4-beea-4f02-9a7a-c0e04d1648f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943335362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2943335362
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1582895927
Short name T567
Test name
Test status
Simulation time 17567571 ps
CPU time 0.56 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:10 AM PDT 24
Peak memory 181528 kb
Host smart-5b33b7af-cefd-433d-8668-b5bb001eef55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582895927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1582895927
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2373258103
Short name T94
Test name
Test status
Simulation time 33310003 ps
CPU time 0.8 seconds
Started Jul 02 09:05:06 AM PDT 24
Finished Jul 02 09:05:07 AM PDT 24
Peak memory 192848 kb
Host smart-0b2aeef2-15b2-4f3d-84a6-b771386c78ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373258103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2373258103
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2588254560
Short name T531
Test name
Test status
Simulation time 156481215 ps
CPU time 3.01 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 197112 kb
Host smart-bc9c175c-17ac-4591-b94a-27c5edbf8dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588254560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2588254560
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3187584762
Short name T547
Test name
Test status
Simulation time 214958521 ps
CPU time 1.49 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:11 AM PDT 24
Peak memory 195084 kb
Host smart-14c32519-2af1-4750-b574-92d56544e00b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187584762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3187584762
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1924375276
Short name T514
Test name
Test status
Simulation time 36058964 ps
CPU time 0.88 seconds
Started Jul 02 09:05:13 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 196884 kb
Host smart-db058d8d-d1fa-4f76-b4a5-5d949779506e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924375276 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1924375276
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1903946870
Short name T499
Test name
Test status
Simulation time 38806844 ps
CPU time 0.57 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:10 AM PDT 24
Peak memory 181672 kb
Host smart-678a403b-a02b-4ec3-9fad-75aa69d71a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903946870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1903946870
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2947555083
Short name T560
Test name
Test status
Simulation time 35854984 ps
CPU time 0.59 seconds
Started Jul 02 09:05:12 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 181652 kb
Host smart-e1bd2a9e-c726-410c-ab59-2c5e9f8b9220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947555083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2947555083
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4072311763
Short name T562
Test name
Test status
Simulation time 35004878 ps
CPU time 0.74 seconds
Started Jul 02 09:05:06 AM PDT 24
Finished Jul 02 09:05:08 AM PDT 24
Peak memory 191268 kb
Host smart-dd7a5bb0-b35c-4515-8f1a-32ff2a9d63bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072311763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4072311763
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4009458034
Short name T486
Test name
Test status
Simulation time 24908539 ps
CPU time 1.16 seconds
Started Jul 02 09:05:09 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 197120 kb
Host smart-9cc7223c-9e14-4e64-a72b-2a63cb7a5006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009458034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4009458034
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4006989155
Short name T571
Test name
Test status
Simulation time 98430126 ps
CPU time 1.29 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:14 AM PDT 24
Peak memory 194760 kb
Host smart-54275442-e296-4f5f-b0e6-4dc47d4a6e77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006989155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4006989155
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.571043111
Short name T511
Test name
Test status
Simulation time 199445749 ps
CPU time 1.11 seconds
Started Jul 02 09:05:09 AM PDT 24
Finished Jul 02 09:05:11 AM PDT 24
Peak memory 196952 kb
Host smart-f024d62d-9774-4d39-bc42-860c2adb81eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571043111 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.571043111
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1820491312
Short name T79
Test name
Test status
Simulation time 11377124 ps
CPU time 0.56 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 182316 kb
Host smart-00d5ba64-11b5-4a75-9e5d-9e71e7fc00d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820491312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1820491312
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2884802552
Short name T564
Test name
Test status
Simulation time 17131393 ps
CPU time 0.57 seconds
Started Jul 02 09:05:11 AM PDT 24
Finished Jul 02 09:05:14 AM PDT 24
Peak memory 182200 kb
Host smart-91d34878-5f32-4b44-82b5-2892bb5d50d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884802552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2884802552
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4179633723
Short name T512
Test name
Test status
Simulation time 184597695 ps
CPU time 0.77 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 192904 kb
Host smart-7ab9180b-d264-46f4-8a0a-8434eda8e59d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179633723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.4179633723
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1509829344
Short name T482
Test name
Test status
Simulation time 156454314 ps
CPU time 2.15 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:12 AM PDT 24
Peak memory 197088 kb
Host smart-4400a710-a274-44fe-9ace-648d96f5825b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509829344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1509829344
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.812935350
Short name T570
Test name
Test status
Simulation time 252117162 ps
CPU time 0.93 seconds
Started Jul 02 09:05:12 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 193196 kb
Host smart-c7c4337b-3672-40f7-895f-5947439d31a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812935350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.812935350
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2394318988
Short name T515
Test name
Test status
Simulation time 145382879 ps
CPU time 0.7 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 194688 kb
Host smart-4ff544d1-69bb-4802-b133-1f187ceb98f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394318988 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2394318988
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.900651278
Short name T88
Test name
Test status
Simulation time 14314128 ps
CPU time 0.58 seconds
Started Jul 02 09:05:13 AM PDT 24
Finished Jul 02 09:05:16 AM PDT 24
Peak memory 182320 kb
Host smart-4a715362-3380-4e52-8307-79b247de924c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900651278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.900651278
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4286138076
Short name T565
Test name
Test status
Simulation time 84708669 ps
CPU time 0.53 seconds
Started Jul 02 09:05:07 AM PDT 24
Finished Jul 02 09:05:09 AM PDT 24
Peak memory 181868 kb
Host smart-c904013f-d30f-4638-9a83-58366fb6acc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286138076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4286138076
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.527425261
Short name T492
Test name
Test status
Simulation time 42296602 ps
CPU time 0.62 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 190996 kb
Host smart-34eb13d6-7078-4448-a20e-24c0a7bbb593
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527425261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.527425261
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2177721127
Short name T503
Test name
Test status
Simulation time 30977480 ps
CPU time 1.5 seconds
Started Jul 02 09:05:06 AM PDT 24
Finished Jul 02 09:05:09 AM PDT 24
Peak memory 197108 kb
Host smart-c042d32d-110f-487e-bc8f-916de858d184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177721127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2177721127
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1002439881
Short name T474
Test name
Test status
Simulation time 45188665 ps
CPU time 0.91 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 193508 kb
Host smart-2379975f-6bfb-47ce-b430-8ebcac9ffc4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002439881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1002439881
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3385686202
Short name T532
Test name
Test status
Simulation time 92618462 ps
CPU time 0.73 seconds
Started Jul 02 09:05:12 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 194896 kb
Host smart-c732c5b6-4fed-4afa-9d49-3b2f316f17c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385686202 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3385686202
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2996458148
Short name T52
Test name
Test status
Simulation time 20808611 ps
CPU time 0.59 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:12 AM PDT 24
Peak memory 182336 kb
Host smart-0dc3c7cd-bb78-427c-b2c3-f012b258f63d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996458148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2996458148
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3435682307
Short name T452
Test name
Test status
Simulation time 14753439 ps
CPU time 0.56 seconds
Started Jul 02 09:05:13 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 181672 kb
Host smart-019a1b15-3d56-4a7f-8129-9885b0e53297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435682307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3435682307
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3809977988
Short name T528
Test name
Test status
Simulation time 26845362 ps
CPU time 0.69 seconds
Started Jul 02 09:05:14 AM PDT 24
Finished Jul 02 09:05:17 AM PDT 24
Peak memory 192248 kb
Host smart-b532d0a4-5592-48a2-94d9-e98569b01f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809977988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3809977988
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4242336925
Short name T464
Test name
Test status
Simulation time 46355551 ps
CPU time 1.16 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:10 AM PDT 24
Peak memory 197112 kb
Host smart-47bba5ed-c8a7-4c2d-a84a-05fdaedd3ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242336925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4242336925
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3096969361
Short name T54
Test name
Test status
Simulation time 305921993 ps
CPU time 1.08 seconds
Started Jul 02 09:05:13 AM PDT 24
Finished Jul 02 09:05:16 AM PDT 24
Peak memory 194904 kb
Host smart-f83f6858-1b62-46b2-95e5-ff9cbe4dfb49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096969361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3096969361
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2012977140
Short name T481
Test name
Test status
Simulation time 136730865 ps
CPU time 0.92 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:11 AM PDT 24
Peak memory 196472 kb
Host smart-9ea7e65e-0fdb-4cad-a0b9-93f06b6a089d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012977140 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2012977140
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1618303259
Short name T90
Test name
Test status
Simulation time 37964321 ps
CPU time 0.57 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 182332 kb
Host smart-824d2ce5-f1d1-49ff-8e27-b952f4b86067
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618303259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1618303259
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2127125087
Short name T459
Test name
Test status
Simulation time 51652366 ps
CPU time 0.53 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 182212 kb
Host smart-84837c05-56a3-417e-934d-e584d5658b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127125087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2127125087
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1469633387
Short name T534
Test name
Test status
Simulation time 118459671 ps
CPU time 0.75 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 192780 kb
Host smart-c7e58fe7-fc1f-494e-8d52-104d14fc34c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469633387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1469633387
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4288913759
Short name T497
Test name
Test status
Simulation time 295324915 ps
CPU time 1.66 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 197100 kb
Host smart-882a6f49-879c-4717-998d-45ccec4fbfb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288913759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4288913759
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4214276307
Short name T32
Test name
Test status
Simulation time 30466119 ps
CPU time 0.8 seconds
Started Jul 02 09:05:13 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 194728 kb
Host smart-0d241d2a-284b-448e-a44f-7f1b4cc8ebfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214276307 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4214276307
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3909027172
Short name T51
Test name
Test status
Simulation time 14686024 ps
CPU time 0.56 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:11 AM PDT 24
Peak memory 182300 kb
Host smart-bd4a91b9-515f-43e4-b9cb-701c565a43aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909027172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3909027172
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1394687629
Short name T527
Test name
Test status
Simulation time 61364307 ps
CPU time 0.56 seconds
Started Jul 02 09:05:13 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 182220 kb
Host smart-f33d47eb-159f-42c2-98c4-7ef0c4870438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394687629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1394687629
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.48157307
Short name T537
Test name
Test status
Simulation time 39111584 ps
CPU time 0.81 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:10 AM PDT 24
Peak memory 191256 kb
Host smart-844507ec-1775-492b-b24c-ebf14bfa3355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48157307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_tim
er_same_csr_outstanding.48157307
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1061627763
Short name T491
Test name
Test status
Simulation time 232426767 ps
CPU time 2.91 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:12 AM PDT 24
Peak memory 197120 kb
Host smart-fb89add0-0f5d-4173-a451-c39808c7f103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061627763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1061627763
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3221416103
Short name T530
Test name
Test status
Simulation time 96054485 ps
CPU time 1.13 seconds
Started Jul 02 09:05:09 AM PDT 24
Finished Jul 02 09:05:11 AM PDT 24
Peak memory 194712 kb
Host smart-ddf4ae74-909a-477b-8180-afb2e9dfdcb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221416103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3221416103
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.856170872
Short name T472
Test name
Test status
Simulation time 31490394 ps
CPU time 1.41 seconds
Started Jul 02 09:05:18 AM PDT 24
Finished Jul 02 09:05:21 AM PDT 24
Peak memory 197128 kb
Host smart-23523392-9192-4dcc-9c17-7785dcf186d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856170872 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.856170872
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2280179295
Short name T49
Test name
Test status
Simulation time 41498455 ps
CPU time 0.57 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:23 AM PDT 24
Peak memory 182332 kb
Host smart-8432a5fc-eee4-4583-bace-9770cf872757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280179295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2280179295
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3175198780
Short name T561
Test name
Test status
Simulation time 42135804 ps
CPU time 0.53 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 181684 kb
Host smart-0440cd9a-38f9-4077-af55-eac02474d99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175198780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3175198780
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1933567951
Short name T78
Test name
Test status
Simulation time 55118004 ps
CPU time 0.65 seconds
Started Jul 02 09:05:17 AM PDT 24
Finished Jul 02 09:05:20 AM PDT 24
Peak memory 191592 kb
Host smart-2d773c49-e8b4-44ea-b02b-d094a9ecc5cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933567951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1933567951
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1365328270
Short name T556
Test name
Test status
Simulation time 130745393 ps
CPU time 1.5 seconds
Started Jul 02 09:05:09 AM PDT 24
Finished Jul 02 09:05:12 AM PDT 24
Peak memory 197084 kb
Host smart-d095f672-0703-4c06-8f27-880d5ef8699d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365328270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1365328270
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1806352204
Short name T520
Test name
Test status
Simulation time 407843129 ps
CPU time 1.33 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 194888 kb
Host smart-52a32835-a8ff-4f11-be33-819ae4a54b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806352204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1806352204
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1052340799
Short name T553
Test name
Test status
Simulation time 266820045 ps
CPU time 0.84 seconds
Started Jul 02 09:05:16 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 195600 kb
Host smart-54ba3a6c-f69e-4b47-9a7e-8483727a4c34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052340799 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1052340799
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.972943977
Short name T81
Test name
Test status
Simulation time 78009887 ps
CPU time 0.52 seconds
Started Jul 02 09:05:14 AM PDT 24
Finished Jul 02 09:05:17 AM PDT 24
Peak memory 182312 kb
Host smart-1684d518-1bc6-496d-8b1a-146930474ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972943977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.972943977
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2864629601
Short name T524
Test name
Test status
Simulation time 53417375 ps
CPU time 0.54 seconds
Started Jul 02 09:05:16 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 181664 kb
Host smart-0a756785-c158-4837-86ab-a775b4d697f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864629601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2864629601
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1386121183
Short name T92
Test name
Test status
Simulation time 163675247 ps
CPU time 0.62 seconds
Started Jul 02 09:05:14 AM PDT 24
Finished Jul 02 09:05:16 AM PDT 24
Peak memory 191244 kb
Host smart-d4d64eda-4726-4cba-b69d-84978593f828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386121183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1386121183
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3458600881
Short name T542
Test name
Test status
Simulation time 99619931 ps
CPU time 2.05 seconds
Started Jul 02 09:05:14 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 197068 kb
Host smart-b70e38db-5f26-407c-84e8-5a7c3c93cdee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458600881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3458600881
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3539404395
Short name T518
Test name
Test status
Simulation time 299374339 ps
CPU time 1.04 seconds
Started Jul 02 09:05:16 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 194564 kb
Host smart-83a52963-8a21-4103-8271-a6680f9f651a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539404395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3539404395
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3198291792
Short name T80
Test name
Test status
Simulation time 21000332 ps
CPU time 0.79 seconds
Started Jul 02 09:04:56 AM PDT 24
Finished Jul 02 09:04:57 AM PDT 24
Peak memory 182324 kb
Host smart-1e6e2969-4ea7-40b6-8418-45b3419429f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198291792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3198291792
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1562762585
Short name T510
Test name
Test status
Simulation time 4497192912 ps
CPU time 3.57 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 190736 kb
Host smart-890fbfca-6bbd-4a11-aff2-09a8832edf38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562762585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1562762585
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2724643470
Short name T83
Test name
Test status
Simulation time 16301233 ps
CPU time 0.54 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 182256 kb
Host smart-693b511a-bac2-4dd9-b38e-b9f3244f200f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724643470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2724643470
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3946101466
Short name T473
Test name
Test status
Simulation time 125926738 ps
CPU time 0.73 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:11 AM PDT 24
Peak memory 194292 kb
Host smart-1d895aa7-fb6a-439e-86c4-027f52025922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946101466 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3946101466
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3976471419
Short name T483
Test name
Test status
Simulation time 13169482 ps
CPU time 0.61 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:02 AM PDT 24
Peak memory 182312 kb
Host smart-f4f8e68a-b368-4ce7-84ab-9b73b109419c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976471419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3976471419
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1102590355
Short name T465
Test name
Test status
Simulation time 33442484 ps
CPU time 0.56 seconds
Started Jul 02 09:05:04 AM PDT 24
Finished Jul 02 09:05:06 AM PDT 24
Peak memory 182424 kb
Host smart-3bc9c52d-bc40-4d1f-a822-4d7c15bf76a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102590355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1102590355
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1118321853
Short name T73
Test name
Test status
Simulation time 13302255 ps
CPU time 0.63 seconds
Started Jul 02 09:04:57 AM PDT 24
Finished Jul 02 09:04:59 AM PDT 24
Peak memory 191092 kb
Host smart-39e587fb-4799-4232-b622-b65f69bb1e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118321853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1118321853
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1836730698
Short name T558
Test name
Test status
Simulation time 330400005 ps
CPU time 2.76 seconds
Started Jul 02 09:05:01 AM PDT 24
Finished Jul 02 09:05:06 AM PDT 24
Peak memory 197136 kb
Host smart-b056e402-4205-41ea-aee1-797b4c0ec3b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836730698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1836730698
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2376220266
Short name T98
Test name
Test status
Simulation time 93748425 ps
CPU time 1.12 seconds
Started Jul 02 09:04:57 AM PDT 24
Finished Jul 02 09:04:59 AM PDT 24
Peak memory 194876 kb
Host smart-1f33a082-676e-4eb1-94b2-9ac0fc004c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376220266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2376220266
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1349013449
Short name T488
Test name
Test status
Simulation time 13499428 ps
CPU time 0.54 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:17 AM PDT 24
Peak memory 182160 kb
Host smart-639d145e-6a13-4b71-89ea-cfa54f07386a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349013449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1349013449
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2631345770
Short name T453
Test name
Test status
Simulation time 13989410 ps
CPU time 0.54 seconds
Started Jul 02 09:05:14 AM PDT 24
Finished Jul 02 09:05:17 AM PDT 24
Peak memory 182204 kb
Host smart-12bc12f9-243a-42fc-8614-8695f8f4d1f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631345770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2631345770
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.744960011
Short name T495
Test name
Test status
Simulation time 34663229 ps
CPU time 0.54 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:17 AM PDT 24
Peak memory 182164 kb
Host smart-dc18b0c7-dd08-4f1f-9c96-89532cf0358c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744960011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.744960011
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.390670434
Short name T572
Test name
Test status
Simulation time 15499106 ps
CPU time 0.55 seconds
Started Jul 02 09:05:18 AM PDT 24
Finished Jul 02 09:05:20 AM PDT 24
Peak memory 181884 kb
Host smart-215c464d-e963-4ac0-b010-d82d5f2827c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390670434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.390670434
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3739839478
Short name T504
Test name
Test status
Simulation time 36955006 ps
CPU time 0.54 seconds
Started Jul 02 09:05:18 AM PDT 24
Finished Jul 02 09:05:20 AM PDT 24
Peak memory 181672 kb
Host smart-c20fba68-bb98-4515-8a3d-f6874938f634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739839478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3739839478
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.411104402
Short name T568
Test name
Test status
Simulation time 54064834 ps
CPU time 0.56 seconds
Started Jul 02 09:05:22 AM PDT 24
Finished Jul 02 09:05:24 AM PDT 24
Peak memory 182176 kb
Host smart-c148fdeb-a681-4a87-9438-c333691792c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411104402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.411104402
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.639460928
Short name T505
Test name
Test status
Simulation time 21688841 ps
CPU time 0.57 seconds
Started Jul 02 09:05:14 AM PDT 24
Finished Jul 02 09:05:17 AM PDT 24
Peak memory 182428 kb
Host smart-7647235a-d326-415d-a858-b8a35088e723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639460928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.639460928
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.949552369
Short name T467
Test name
Test status
Simulation time 34770291 ps
CPU time 0.56 seconds
Started Jul 02 09:05:24 AM PDT 24
Finished Jul 02 09:05:25 AM PDT 24
Peak memory 182176 kb
Host smart-176ca180-2d58-4afd-8985-e58f9dc852d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949552369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.949552369
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3534293528
Short name T508
Test name
Test status
Simulation time 35065175 ps
CPU time 0.53 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 181652 kb
Host smart-d9aad816-24c8-4f13-a47b-38ba608f813e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534293528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3534293528
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3934291791
Short name T455
Test name
Test status
Simulation time 35209398 ps
CPU time 0.55 seconds
Started Jul 02 09:05:25 AM PDT 24
Finished Jul 02 09:05:26 AM PDT 24
Peak memory 182140 kb
Host smart-2c62b2c2-73e8-4bd8-9f34-8b8c843c8d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934291791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3934291791
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1900272263
Short name T569
Test name
Test status
Simulation time 240365227 ps
CPU time 0.84 seconds
Started Jul 02 09:05:07 AM PDT 24
Finished Jul 02 09:05:08 AM PDT 24
Peak memory 192056 kb
Host smart-804724ac-8f38-4633-8485-441c07f27ad3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900272263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1900272263
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3621451850
Short name T551
Test name
Test status
Simulation time 1548786539 ps
CPU time 2.53 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:14 AM PDT 24
Peak memory 192240 kb
Host smart-5dfe9b1d-bb39-4db9-82de-75e447175939
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621451850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3621451850
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.689204064
Short name T77
Test name
Test status
Simulation time 42318873 ps
CPU time 0.59 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:03 AM PDT 24
Peak memory 182288 kb
Host smart-dfd856b3-b895-4111-91ae-6760f4210d89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689204064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.689204064
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3300101522
Short name T31
Test name
Test status
Simulation time 24587059 ps
CPU time 1.01 seconds
Started Jul 02 09:05:01 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 196908 kb
Host smart-ae73500e-6848-4081-9274-834685622ffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300101522 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3300101522
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3274428909
Short name T574
Test name
Test status
Simulation time 30312125 ps
CPU time 0.58 seconds
Started Jul 02 09:05:12 AM PDT 24
Finished Jul 02 09:05:14 AM PDT 24
Peak memory 182312 kb
Host smart-5e7fef14-f55b-4ba8-a4ad-a476a7a88a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274428909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3274428909
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.160250574
Short name T489
Test name
Test status
Simulation time 11877478 ps
CPU time 0.54 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:02 AM PDT 24
Peak memory 181868 kb
Host smart-9f5b6578-a99d-4afd-9024-8b5d4da8328d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160250574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.160250574
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1992561594
Short name T506
Test name
Test status
Simulation time 167655065 ps
CPU time 0.89 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:03 AM PDT 24
Peak memory 191292 kb
Host smart-577db998-4baf-4506-8def-bc2a1dfbd2d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992561594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1992561594
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1508155836
Short name T523
Test name
Test status
Simulation time 146123339 ps
CPU time 2.52 seconds
Started Jul 02 09:05:04 AM PDT 24
Finished Jul 02 09:05:08 AM PDT 24
Peak memory 197120 kb
Host smart-632ae9d1-a59b-4669-b6b7-932f9b9228cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508155836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1508155836
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3648107536
Short name T498
Test name
Test status
Simulation time 175428014 ps
CPU time 1.4 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:03 AM PDT 24
Peak memory 195048 kb
Host smart-eb9fc59d-0c55-4ae9-9d6d-893a87d60030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648107536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3648107536
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3321142559
Short name T529
Test name
Test status
Simulation time 14259742 ps
CPU time 0.58 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 182180 kb
Host smart-b1c12651-1bc9-49cb-8b5c-72373b85b4f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321142559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3321142559
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1587244300
Short name T563
Test name
Test status
Simulation time 10730170 ps
CPU time 0.52 seconds
Started Jul 02 09:05:17 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 181708 kb
Host smart-a9e82cfd-c547-4605-8b80-0aa93d227eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587244300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1587244300
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2368749463
Short name T549
Test name
Test status
Simulation time 29120391 ps
CPU time 0.58 seconds
Started Jul 02 09:05:18 AM PDT 24
Finished Jul 02 09:05:20 AM PDT 24
Peak memory 182116 kb
Host smart-114715fb-e13b-4b6f-8c7f-6732ba63aeea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368749463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2368749463
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1131486672
Short name T462
Test name
Test status
Simulation time 15045772 ps
CPU time 0.58 seconds
Started Jul 02 09:05:26 AM PDT 24
Finished Jul 02 09:05:27 AM PDT 24
Peak memory 182208 kb
Host smart-941d6813-f418-40da-9759-394df49f3d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131486672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1131486672
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4199610863
Short name T533
Test name
Test status
Simulation time 20530713 ps
CPU time 0.61 seconds
Started Jul 02 09:05:18 AM PDT 24
Finished Jul 02 09:05:20 AM PDT 24
Peak memory 182136 kb
Host smart-7aa09c5b-fafd-4f29-9298-4ffa114e0b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199610863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4199610863
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2063415715
Short name T469
Test name
Test status
Simulation time 13913750 ps
CPU time 0.55 seconds
Started Jul 02 09:05:16 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 181896 kb
Host smart-8de6515f-031c-4e3e-89fd-78dad88811d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063415715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2063415715
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1590690563
Short name T555
Test name
Test status
Simulation time 49789998 ps
CPU time 0.57 seconds
Started Jul 02 09:05:16 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 181708 kb
Host smart-05a0d1a1-54b7-435a-8f94-1e62d9cf2ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590690563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1590690563
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2390220691
Short name T507
Test name
Test status
Simulation time 116238874 ps
CPU time 0.52 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:23 AM PDT 24
Peak memory 181880 kb
Host smart-821d9eca-e639-474c-9629-d6a853cdd19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390220691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2390220691
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1485617357
Short name T470
Test name
Test status
Simulation time 13689889 ps
CPU time 0.54 seconds
Started Jul 02 09:05:17 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 181884 kb
Host smart-5f3f03f2-6513-453e-b453-6792bca30bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485617357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1485617357
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1831508142
Short name T517
Test name
Test status
Simulation time 50887941 ps
CPU time 0.53 seconds
Started Jul 02 09:05:19 AM PDT 24
Finished Jul 02 09:05:21 AM PDT 24
Peak memory 181644 kb
Host smart-f8ffe0cc-78c1-47bb-96fe-471b2c18235e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831508142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1831508142
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2085732533
Short name T85
Test name
Test status
Simulation time 121357330 ps
CPU time 0.82 seconds
Started Jul 02 09:04:56 AM PDT 24
Finished Jul 02 09:04:58 AM PDT 24
Peak memory 192320 kb
Host smart-b1db329d-bae2-4bf6-9cc4-260f3cf60939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085732533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2085732533
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3490879759
Short name T87
Test name
Test status
Simulation time 124021829 ps
CPU time 2.31 seconds
Started Jul 02 09:05:01 AM PDT 24
Finished Jul 02 09:05:05 AM PDT 24
Peak memory 190636 kb
Host smart-f544a5fc-aa32-48cb-9d79-020b404fa7ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490879759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3490879759
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.596995691
Short name T509
Test name
Test status
Simulation time 38804862 ps
CPU time 0.54 seconds
Started Jul 02 09:04:57 AM PDT 24
Finished Jul 02 09:04:59 AM PDT 24
Peak memory 182292 kb
Host smart-54147964-59d6-4b2b-8cc2-fe4ba2a1a7cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596995691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.596995691
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.850349683
Short name T463
Test name
Test status
Simulation time 276836512 ps
CPU time 0.89 seconds
Started Jul 02 09:05:02 AM PDT 24
Finished Jul 02 09:05:05 AM PDT 24
Peak memory 196932 kb
Host smart-5a966b7d-4194-48e4-a17a-0a3f5a0b5b85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850349683 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.850349683
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3182525341
Short name T490
Test name
Test status
Simulation time 22880951 ps
CPU time 0.59 seconds
Started Jul 02 09:05:01 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 191508 kb
Host smart-e4ecbf01-505b-4b09-b413-96a5d757b0c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182525341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3182525341
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.894062572
Short name T538
Test name
Test status
Simulation time 17568193 ps
CPU time 0.56 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:02 AM PDT 24
Peak memory 182136 kb
Host smart-9009d3b1-d640-4d33-9f75-28afbeb5f7c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894062572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.894062572
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3068844194
Short name T554
Test name
Test status
Simulation time 19739031 ps
CPU time 0.78 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:03 AM PDT 24
Peak memory 192980 kb
Host smart-c532da18-a649-4cea-a403-cae428728618
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068844194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3068844194
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2716717289
Short name T496
Test name
Test status
Simulation time 36187255 ps
CPU time 0.85 seconds
Started Jul 02 09:04:59 AM PDT 24
Finished Jul 02 09:05:01 AM PDT 24
Peak memory 196020 kb
Host smart-d76925b3-7451-45f7-8758-4b85ac70f168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716717289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2716717289
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3859970794
Short name T480
Test name
Test status
Simulation time 85341660 ps
CPU time 1.08 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 194740 kb
Host smart-3e6cda49-aca5-48b5-a4c2-014595223dac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859970794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3859970794
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2922083983
Short name T484
Test name
Test status
Simulation time 17436006 ps
CPU time 0.54 seconds
Started Jul 02 09:05:17 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 181692 kb
Host smart-13d0309b-fd43-4f40-86fe-6e5ad35253a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922083983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2922083983
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3878210969
Short name T478
Test name
Test status
Simulation time 15269215 ps
CPU time 0.54 seconds
Started Jul 02 09:05:17 AM PDT 24
Finished Jul 02 09:05:20 AM PDT 24
Peak memory 181676 kb
Host smart-f6e65097-56fd-4531-ac5b-ec8757607ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878210969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3878210969
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1947783204
Short name T516
Test name
Test status
Simulation time 22545310 ps
CPU time 0.56 seconds
Started Jul 02 09:05:23 AM PDT 24
Finished Jul 02 09:05:25 AM PDT 24
Peak memory 181716 kb
Host smart-df13a9a2-75ac-40b3-b3e5-3baf24215373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947783204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1947783204
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3755789734
Short name T494
Test name
Test status
Simulation time 43739796 ps
CPU time 0.55 seconds
Started Jul 02 09:05:18 AM PDT 24
Finished Jul 02 09:05:20 AM PDT 24
Peak memory 182196 kb
Host smart-739a179a-f676-4314-86bf-c6a651973475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755789734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3755789734
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2762016223
Short name T457
Test name
Test status
Simulation time 164414497 ps
CPU time 0.57 seconds
Started Jul 02 09:05:24 AM PDT 24
Finished Jul 02 09:05:25 AM PDT 24
Peak memory 182252 kb
Host smart-913158a4-3310-4f7c-9baa-d6262c484cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762016223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2762016223
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2808661641
Short name T535
Test name
Test status
Simulation time 24082208 ps
CPU time 0.56 seconds
Started Jul 02 09:05:22 AM PDT 24
Finished Jul 02 09:05:23 AM PDT 24
Peak memory 182212 kb
Host smart-674be8c2-37b3-42a2-bf24-e5d33b00f2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808661641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2808661641
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1274976281
Short name T500
Test name
Test status
Simulation time 19967520 ps
CPU time 0.57 seconds
Started Jul 02 09:05:22 AM PDT 24
Finished Jul 02 09:05:24 AM PDT 24
Peak memory 181672 kb
Host smart-13b71068-559c-450c-8814-3dab3383108f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274976281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1274976281
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1116120014
Short name T526
Test name
Test status
Simulation time 16265754 ps
CPU time 0.54 seconds
Started Jul 02 09:05:21 AM PDT 24
Finished Jul 02 09:05:23 AM PDT 24
Peak memory 181680 kb
Host smart-d52cd983-253c-479d-b12b-a4715f8510db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116120014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1116120014
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3306690088
Short name T546
Test name
Test status
Simulation time 21154724 ps
CPU time 0.55 seconds
Started Jul 02 09:05:17 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 181672 kb
Host smart-793eb321-717a-4d3a-9149-54e67a921162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306690088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3306690088
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2388492473
Short name T501
Test name
Test status
Simulation time 17773200 ps
CPU time 0.57 seconds
Started Jul 02 09:05:19 AM PDT 24
Finished Jul 02 09:05:21 AM PDT 24
Peak memory 182228 kb
Host smart-909d5e73-3ffd-4fa6-80da-06d2531ac12b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388492473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2388492473
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2589415268
Short name T460
Test name
Test status
Simulation time 63124598 ps
CPU time 0.84 seconds
Started Jul 02 09:04:59 AM PDT 24
Finished Jul 02 09:05:02 AM PDT 24
Peak memory 196080 kb
Host smart-fe8ac9ac-5625-49ac-8bd6-88ae4d2472e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589415268 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2589415268
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1854928124
Short name T84
Test name
Test status
Simulation time 13789673 ps
CPU time 0.57 seconds
Started Jul 02 09:05:02 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 182292 kb
Host smart-6dda6ebb-84f0-47ca-b4d7-0df717d155c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854928124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1854928124
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1359174942
Short name T539
Test name
Test status
Simulation time 11760684 ps
CPU time 0.58 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:09 AM PDT 24
Peak memory 182212 kb
Host smart-f3a8d507-61d7-4c4c-9568-94bc426d1efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359174942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1359174942
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3483672077
Short name T50
Test name
Test status
Simulation time 72080590 ps
CPU time 0.63 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:10 AM PDT 24
Peak memory 191564 kb
Host smart-05b46d6e-9f67-4ebf-ab97-e78ac408dc2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483672077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3483672077
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.930404087
Short name T466
Test name
Test status
Simulation time 44589968 ps
CPU time 2.1 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:03 AM PDT 24
Peak memory 196928 kb
Host smart-a28f4ae7-815d-471d-82b7-bb35210b1df6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930404087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.930404087
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3947138571
Short name T550
Test name
Test status
Simulation time 322903039 ps
CPU time 1.07 seconds
Started Jul 02 09:04:57 AM PDT 24
Finished Jul 02 09:04:59 AM PDT 24
Peak memory 183008 kb
Host smart-44b150f7-025a-4445-8db0-c71307e0425f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947138571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3947138571
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2279816138
Short name T559
Test name
Test status
Simulation time 140421221 ps
CPU time 0.89 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 196216 kb
Host smart-c0e3b189-255c-42ce-9577-a3f9626d0231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279816138 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2279816138
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.609229548
Short name T471
Test name
Test status
Simulation time 32547995 ps
CPU time 0.51 seconds
Started Jul 02 09:05:02 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 182332 kb
Host smart-583886b4-de90-4bb5-89dc-8d176fa8b708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609229548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.609229548
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.477736848
Short name T493
Test name
Test status
Simulation time 29710071 ps
CPU time 0.53 seconds
Started Jul 02 09:05:02 AM PDT 24
Finished Jul 02 09:05:05 AM PDT 24
Peak memory 182176 kb
Host smart-0b08de57-7a12-4589-b259-5c6a8714a5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477736848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.477736848
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3767028883
Short name T485
Test name
Test status
Simulation time 19769783 ps
CPU time 0.64 seconds
Started Jul 02 09:05:02 AM PDT 24
Finished Jul 02 09:05:05 AM PDT 24
Peak memory 191696 kb
Host smart-8ce85ecf-160c-4e88-85ef-699910077c74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767028883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3767028883
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.388031942
Short name T557
Test name
Test status
Simulation time 52937213 ps
CPU time 2.39 seconds
Started Jul 02 09:05:04 AM PDT 24
Finished Jul 02 09:05:08 AM PDT 24
Peak memory 197100 kb
Host smart-3bed3b19-b6c2-47c6-9938-63d59a2f1f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388031942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.388031942
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1645790622
Short name T536
Test name
Test status
Simulation time 532555372 ps
CPU time 1.28 seconds
Started Jul 02 09:05:14 AM PDT 24
Finished Jul 02 09:05:18 AM PDT 24
Peak memory 194668 kb
Host smart-ca1d11a4-d704-4f1e-ac5d-f5e809e8d211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645790622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1645790622
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2570644361
Short name T53
Test name
Test status
Simulation time 25348201 ps
CPU time 0.76 seconds
Started Jul 02 09:05:00 AM PDT 24
Finished Jul 02 09:05:03 AM PDT 24
Peak memory 194888 kb
Host smart-1db31bcc-f2bb-48f0-a19b-f94ed80f855a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570644361 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2570644361
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1981620728
Short name T476
Test name
Test status
Simulation time 19022540 ps
CPU time 0.54 seconds
Started Jul 02 09:05:10 AM PDT 24
Finished Jul 02 09:05:13 AM PDT 24
Peak memory 182292 kb
Host smart-6f42b8ce-958f-41c6-8862-aafd3ad8addc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981620728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1981620728
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2947683465
Short name T519
Test name
Test status
Simulation time 146506334 ps
CPU time 0.56 seconds
Started Jul 02 09:05:12 AM PDT 24
Finished Jul 02 09:05:14 AM PDT 24
Peak memory 182176 kb
Host smart-39355589-f56c-4b4e-b101-1bd8195833b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947683465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2947683465
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1923173915
Short name T56
Test name
Test status
Simulation time 61851266 ps
CPU time 0.6 seconds
Started Jul 02 09:05:02 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 191560 kb
Host smart-5b659713-059e-4c0c-938c-a66fe16e6a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923173915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1923173915
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3501078841
Short name T458
Test name
Test status
Simulation time 94573127 ps
CPU time 2.28 seconds
Started Jul 02 09:05:15 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 197096 kb
Host smart-23f528c0-b0b9-4d2a-a9b0-1fae85bdfb25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501078841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3501078841
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.247651456
Short name T573
Test name
Test status
Simulation time 71261102 ps
CPU time 1.11 seconds
Started Jul 02 09:05:16 AM PDT 24
Finished Jul 02 09:05:19 AM PDT 24
Peak memory 182708 kb
Host smart-b734c67f-50f8-4b19-9e4c-8402c0c3f8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247651456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.247651456
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1270650050
Short name T461
Test name
Test status
Simulation time 46856726 ps
CPU time 1.12 seconds
Started Jul 02 09:05:04 AM PDT 24
Finished Jul 02 09:05:06 AM PDT 24
Peak memory 197064 kb
Host smart-a9b7f319-7a11-4f8b-9f4a-389ca6b87dcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270650050 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1270650050
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3834900033
Short name T75
Test name
Test status
Simulation time 68269607 ps
CPU time 0.56 seconds
Started Jul 02 09:05:12 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 182016 kb
Host smart-d9dae9f5-b3a3-402e-bd71-c5caa974ebf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834900033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3834900033
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3175900962
Short name T477
Test name
Test status
Simulation time 16824803 ps
CPU time 0.57 seconds
Started Jul 02 09:05:09 AM PDT 24
Finished Jul 02 09:05:11 AM PDT 24
Peak memory 182244 kb
Host smart-415c3997-a536-4447-ad66-644e0a482d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175900962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3175900962
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2687531087
Short name T76
Test name
Test status
Simulation time 212757799 ps
CPU time 0.79 seconds
Started Jul 02 09:05:01 AM PDT 24
Finished Jul 02 09:05:04 AM PDT 24
Peak memory 192892 kb
Host smart-b25388ab-d700-4217-8454-07012c430731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687531087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2687531087
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3392634778
Short name T543
Test name
Test status
Simulation time 23989263 ps
CPU time 1.09 seconds
Started Jul 02 09:05:01 AM PDT 24
Finished Jul 02 09:05:05 AM PDT 24
Peak memory 196972 kb
Host smart-e16831ad-3b87-42d7-aed6-92f2d083af5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392634778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3392634778
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1251974506
Short name T97
Test name
Test status
Simulation time 275537730 ps
CPU time 1.1 seconds
Started Jul 02 09:05:04 AM PDT 24
Finished Jul 02 09:05:06 AM PDT 24
Peak memory 182960 kb
Host smart-1d68f71d-48be-4bf5-b78b-658f252e0824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251974506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1251974506
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2905520791
Short name T548
Test name
Test status
Simulation time 134442734 ps
CPU time 0.95 seconds
Started Jul 02 09:05:20 AM PDT 24
Finished Jul 02 09:05:21 AM PDT 24
Peak memory 196940 kb
Host smart-d119ee5d-7902-4501-8c3e-8f008f946125
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905520791 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2905520791
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1675196615
Short name T521
Test name
Test status
Simulation time 23782142 ps
CPU time 0.57 seconds
Started Jul 02 09:05:13 AM PDT 24
Finished Jul 02 09:05:15 AM PDT 24
Peak memory 182304 kb
Host smart-4fabeb40-08ac-451b-b4fe-ec7eff85f795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675196615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1675196615
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2144466027
Short name T475
Test name
Test status
Simulation time 18143090 ps
CPU time 0.6 seconds
Started Jul 02 09:05:08 AM PDT 24
Finished Jul 02 09:05:10 AM PDT 24
Peak memory 182204 kb
Host smart-fbf7d4f0-7b3f-4a95-9947-088c9ad36fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144466027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2144466027
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3639108836
Short name T95
Test name
Test status
Simulation time 29373783 ps
CPU time 0.68 seconds
Started Jul 02 09:05:05 AM PDT 24
Finished Jul 02 09:05:07 AM PDT 24
Peak memory 192940 kb
Host smart-54796c2c-70b0-47f5-97ea-b51e4e6560cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639108836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3639108836
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3168628904
Short name T456
Test name
Test status
Simulation time 215576094 ps
CPU time 0.99 seconds
Started Jul 02 09:05:05 AM PDT 24
Finished Jul 02 09:05:07 AM PDT 24
Peak memory 196876 kb
Host smart-1416cdbd-4d6d-4ef7-b503-3f955e74a177
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168628904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3168628904
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4048312735
Short name T96
Test name
Test status
Simulation time 118010267 ps
CPU time 1.1 seconds
Started Jul 02 09:05:05 AM PDT 24
Finished Jul 02 09:05:07 AM PDT 24
Peak memory 194856 kb
Host smart-0ec1a0d1-d2d9-465d-ad9f-0e2a00507f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048312735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4048312735
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1861909865
Short name T404
Test name
Test status
Simulation time 777924676078 ps
CPU time 431.32 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:35:15 AM PDT 24
Peak memory 183164 kb
Host smart-c10882b5-c1cf-4014-958d-17d329a5dfbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861909865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1861909865
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.682921288
Short name T413
Test name
Test status
Simulation time 513867092012 ps
CPU time 168.01 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:30:50 AM PDT 24
Peak memory 183140 kb
Host smart-dc9b9f0d-14f5-4289-b71b-6ad3c43fb68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682921288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.682921288
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.4081203344
Short name T255
Test name
Test status
Simulation time 445140126672 ps
CPU time 316.44 seconds
Started Jul 02 09:27:59 AM PDT 24
Finished Jul 02 09:33:16 AM PDT 24
Peak memory 191384 kb
Host smart-55487f22-46d8-4403-97d9-86f28973433b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081203344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4081203344
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2290270681
Short name T359
Test name
Test status
Simulation time 356072915736 ps
CPU time 198.25 seconds
Started Jul 02 09:27:56 AM PDT 24
Finished Jul 02 09:31:14 AM PDT 24
Peak memory 183196 kb
Host smart-675bff19-733b-4df5-86c2-7e03574dc507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290270681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2290270681
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1524967170
Short name T333
Test name
Test status
Simulation time 286357882927 ps
CPU time 432.16 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:35:11 AM PDT 24
Peak memory 191356 kb
Host smart-d4500615-ec1b-48cb-8ce5-ccbbe5e8095c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524967170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1524967170
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2602419274
Short name T132
Test name
Test status
Simulation time 80465086331 ps
CPU time 549.84 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:37:08 AM PDT 24
Peak memory 195060 kb
Host smart-c40faba8-362c-4caf-8e6f-952dfdeabf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602419274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2602419274
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.736507231
Short name T15
Test name
Test status
Simulation time 35894811 ps
CPU time 0.74 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:28:00 AM PDT 24
Peak memory 213376 kb
Host smart-08cb8479-4002-46fd-8117-630b6bea4c9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736507231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.736507231
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.4116907172
Short name T169
Test name
Test status
Simulation time 71768422304 ps
CPU time 133.19 seconds
Started Jul 02 09:27:59 AM PDT 24
Finished Jul 02 09:30:13 AM PDT 24
Peak memory 191280 kb
Host smart-6514fb3a-58cd-437e-9f64-915425726b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116907172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
4116907172
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2905501531
Short name T392
Test name
Test status
Simulation time 2176821432 ps
CPU time 2.55 seconds
Started Jul 02 09:28:04 AM PDT 24
Finished Jul 02 09:28:07 AM PDT 24
Peak memory 183132 kb
Host smart-55ba259a-669d-43ec-b376-a82c3e0cc914
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905501531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2905501531
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1467995416
Short name T388
Test name
Test status
Simulation time 176831773300 ps
CPU time 65.89 seconds
Started Jul 02 09:28:09 AM PDT 24
Finished Jul 02 09:29:15 AM PDT 24
Peak memory 183180 kb
Host smart-dae9a4e6-8990-422c-bf48-fd00296d8339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467995416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1467995416
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1007866212
Short name T143
Test name
Test status
Simulation time 131494406489 ps
CPU time 184.37 seconds
Started Jul 02 09:28:06 AM PDT 24
Finished Jul 02 09:31:11 AM PDT 24
Peak memory 191308 kb
Host smart-3af9c989-b0d6-44ec-8803-74020c4d2761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007866212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1007866212
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3739549447
Short name T409
Test name
Test status
Simulation time 41201607224 ps
CPU time 55.21 seconds
Started Jul 02 09:28:06 AM PDT 24
Finished Jul 02 09:29:02 AM PDT 24
Peak memory 192056 kb
Host smart-89df7832-d0f9-4ba3-a055-e59d7c88bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739549447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3739549447
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3628824218
Short name T374
Test name
Test status
Simulation time 35332084114 ps
CPU time 44.99 seconds
Started Jul 02 09:28:06 AM PDT 24
Finished Jul 02 09:28:52 AM PDT 24
Peak memory 183120 kb
Host smart-799dddd8-bf2c-4a56-8d24-ea7c1d6ee822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628824218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3628824218
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.1218710475
Short name T261
Test name
Test status
Simulation time 81472220980 ps
CPU time 515.27 seconds
Started Jul 02 09:29:37 AM PDT 24
Finished Jul 02 09:38:12 AM PDT 24
Peak memory 183128 kb
Host smart-464d5f00-6f76-46b8-ada3-8f3f2c33c4c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218710475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1218710475
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1877036854
Short name T233
Test name
Test status
Simulation time 102643366087 ps
CPU time 104.89 seconds
Started Jul 02 09:29:39 AM PDT 24
Finished Jul 02 09:31:25 AM PDT 24
Peak memory 191332 kb
Host smart-8e0d9fe2-88a2-4d9a-be2c-03f5b636786c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877036854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1877036854
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.214426694
Short name T317
Test name
Test status
Simulation time 208430566885 ps
CPU time 151.7 seconds
Started Jul 02 09:29:40 AM PDT 24
Finished Jul 02 09:32:12 AM PDT 24
Peak memory 183068 kb
Host smart-5bb65c8a-d2a4-415c-b204-e619db206c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214426694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.214426694
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2300826212
Short name T301
Test name
Test status
Simulation time 52012257983 ps
CPU time 66.85 seconds
Started Jul 02 09:29:43 AM PDT 24
Finished Jul 02 09:30:50 AM PDT 24
Peak memory 183140 kb
Host smart-4c38c0d8-4000-4cdf-91ef-af088f4dd7ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300826212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2300826212
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1702005816
Short name T316
Test name
Test status
Simulation time 9966684257 ps
CPU time 5.43 seconds
Started Jul 02 09:29:44 AM PDT 24
Finished Jul 02 09:29:50 AM PDT 24
Peak memory 183124 kb
Host smart-e5fd27ab-4c01-4d10-aedb-504c8af43283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702005816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1702005816
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.193201755
Short name T300
Test name
Test status
Simulation time 5687427818 ps
CPU time 2.91 seconds
Started Jul 02 09:29:44 AM PDT 24
Finished Jul 02 09:29:48 AM PDT 24
Peak memory 183144 kb
Host smart-23933af1-2b35-423c-bb18-7838c4b06394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193201755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.193201755
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.417008531
Short name T240
Test name
Test status
Simulation time 98298430600 ps
CPU time 172.19 seconds
Started Jul 02 09:28:09 AM PDT 24
Finished Jul 02 09:31:02 AM PDT 24
Peak memory 183124 kb
Host smart-c3152d4f-43e4-44b7-a13f-a9d62c83050c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417008531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.417008531
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2420779966
Short name T381
Test name
Test status
Simulation time 186746553494 ps
CPU time 240.21 seconds
Started Jul 02 09:28:05 AM PDT 24
Finished Jul 02 09:32:06 AM PDT 24
Peak memory 183184 kb
Host smart-854103dc-d23d-4765-a939-579a4a5682fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420779966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2420779966
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2501388293
Short name T399
Test name
Test status
Simulation time 102388960 ps
CPU time 0.58 seconds
Started Jul 02 09:28:06 AM PDT 24
Finished Jul 02 09:28:07 AM PDT 24
Peak memory 182996 kb
Host smart-1aeca482-621f-41b2-aa4d-36515d4c4b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501388293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2501388293
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2430109197
Short name T185
Test name
Test status
Simulation time 2632135304759 ps
CPU time 532.1 seconds
Started Jul 02 09:29:48 AM PDT 24
Finished Jul 02 09:38:41 AM PDT 24
Peak memory 191360 kb
Host smart-27c6c525-dc49-449e-b73d-46bb9674fc54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430109197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2430109197
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.937353140
Short name T232
Test name
Test status
Simulation time 195108971015 ps
CPU time 161.01 seconds
Started Jul 02 09:29:53 AM PDT 24
Finished Jul 02 09:32:35 AM PDT 24
Peak memory 193592 kb
Host smart-1c5c98ab-24e2-4199-83b2-76c23260c24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937353140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.937353140
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1736488532
Short name T274
Test name
Test status
Simulation time 136095337350 ps
CPU time 525.15 seconds
Started Jul 02 09:29:49 AM PDT 24
Finished Jul 02 09:38:34 AM PDT 24
Peak memory 191364 kb
Host smart-62ac1ae4-a416-4f49-999d-2209df96aa5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736488532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1736488532
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3834293916
Short name T418
Test name
Test status
Simulation time 81858971883 ps
CPU time 78.24 seconds
Started Jul 02 09:29:48 AM PDT 24
Finished Jul 02 09:31:07 AM PDT 24
Peak memory 183104 kb
Host smart-406dc4c0-768e-4e26-8811-6cb237ff98b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834293916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3834293916
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2777595849
Short name T350
Test name
Test status
Simulation time 111967091712 ps
CPU time 547.69 seconds
Started Jul 02 09:29:48 AM PDT 24
Finished Jul 02 09:38:56 AM PDT 24
Peak memory 191324 kb
Host smart-b4ba5c75-e895-496a-86be-8cadfa2991ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777595849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2777595849
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.6973267
Short name T215
Test name
Test status
Simulation time 49899247102 ps
CPU time 454.82 seconds
Started Jul 02 09:29:53 AM PDT 24
Finished Jul 02 09:37:29 AM PDT 24
Peak memory 194916 kb
Host smart-c66eacdf-bfed-437b-abd0-aa859dcb31cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6973267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.6973267
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.342962748
Short name T292
Test name
Test status
Simulation time 265564072617 ps
CPU time 441.55 seconds
Started Jul 02 09:29:51 AM PDT 24
Finished Jul 02 09:37:13 AM PDT 24
Peak memory 191344 kb
Host smart-da9236b5-f7f7-4513-8188-f1d5511c4529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342962748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.342962748
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.3847247945
Short name T421
Test name
Test status
Simulation time 127199732357 ps
CPU time 269.62 seconds
Started Jul 02 09:28:10 AM PDT 24
Finished Jul 02 09:32:41 AM PDT 24
Peak memory 191540 kb
Host smart-fc07768c-6e7a-470b-9920-d3c53a667919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847247945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3847247945
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3189427638
Short name T425
Test name
Test status
Simulation time 57277848848 ps
CPU time 83.95 seconds
Started Jul 02 09:28:09 AM PDT 24
Finished Jul 02 09:29:33 AM PDT 24
Peak memory 183140 kb
Host smart-dde4c6bc-2a08-4800-b076-871acfeb2b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189427638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3189427638
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.695077549
Short name T218
Test name
Test status
Simulation time 184018397251 ps
CPU time 1978.69 seconds
Started Jul 02 09:29:50 AM PDT 24
Finished Jul 02 10:02:49 AM PDT 24
Peak memory 195024 kb
Host smart-7127be94-d1b6-42d2-ad43-4e064bcccf47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695077549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.695077549
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3613421196
Short name T212
Test name
Test status
Simulation time 541819691064 ps
CPU time 433.59 seconds
Started Jul 02 09:29:50 AM PDT 24
Finished Jul 02 09:37:04 AM PDT 24
Peak memory 191328 kb
Host smart-5feb11c1-62d4-40d1-b31b-2e5a989e3a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613421196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3613421196
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3642811043
Short name T166
Test name
Test status
Simulation time 271696661666 ps
CPU time 705.51 seconds
Started Jul 02 09:29:51 AM PDT 24
Finished Jul 02 09:41:37 AM PDT 24
Peak memory 191356 kb
Host smart-5e3fb34c-2ec5-47a5-8260-693fa8eb9045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642811043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3642811043
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.4021992612
Short name T164
Test name
Test status
Simulation time 146436518493 ps
CPU time 428.71 seconds
Started Jul 02 09:29:55 AM PDT 24
Finished Jul 02 09:37:04 AM PDT 24
Peak memory 191364 kb
Host smart-8b6583b2-bdb0-428c-8bef-adce614a88bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021992612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.4021992612
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2706219077
Short name T329
Test name
Test status
Simulation time 586922194636 ps
CPU time 286.23 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 09:34:45 AM PDT 24
Peak memory 191348 kb
Host smart-6cffd20d-56ac-4aed-b9b7-3b871fb4c2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706219077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2706219077
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.82581086
Short name T141
Test name
Test status
Simulation time 173238835969 ps
CPU time 123.11 seconds
Started Jul 02 09:29:54 AM PDT 24
Finished Jul 02 09:31:57 AM PDT 24
Peak memory 183172 kb
Host smart-eedb3dee-1374-401b-9a0b-b94d5bc067f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82581086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.82581086
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1151551254
Short name T246
Test name
Test status
Simulation time 749214018653 ps
CPU time 1076.26 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 09:47:54 AM PDT 24
Peak memory 191340 kb
Host smart-ff6fd005-1a01-4a33-8c1f-8ed04cb42967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151551254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1151551254
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3981776675
Short name T445
Test name
Test status
Simulation time 847512942386 ps
CPU time 394.91 seconds
Started Jul 02 09:28:10 AM PDT 24
Finished Jul 02 09:34:46 AM PDT 24
Peak memory 183164 kb
Host smart-ce4e0ea6-4e9d-4537-8a2e-7b35c93058d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981776675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3981776675
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1236552715
Short name T8
Test name
Test status
Simulation time 379253322190 ps
CPU time 168.88 seconds
Started Jul 02 09:28:10 AM PDT 24
Finished Jul 02 09:31:00 AM PDT 24
Peak memory 183176 kb
Host smart-b65b7021-531c-43a5-84f4-2700d266f312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236552715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1236552715
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2139627486
Short name T136
Test name
Test status
Simulation time 134665503545 ps
CPU time 376.54 seconds
Started Jul 02 09:28:11 AM PDT 24
Finished Jul 02 09:34:28 AM PDT 24
Peak memory 191548 kb
Host smart-878ee8e2-66e4-4784-a32e-ba8d398e72fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139627486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2139627486
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2066443907
Short name T21
Test name
Test status
Simulation time 36503512059 ps
CPU time 52.59 seconds
Started Jul 02 09:28:08 AM PDT 24
Finished Jul 02 09:29:01 AM PDT 24
Peak memory 191392 kb
Host smart-5ba66ac2-50a2-447f-9467-936d953197e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066443907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2066443907
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3324428211
Short name T406
Test name
Test status
Simulation time 33191532102 ps
CPU time 47.54 seconds
Started Jul 02 09:28:12 AM PDT 24
Finished Jul 02 09:29:00 AM PDT 24
Peak memory 183076 kb
Host smart-68a186ab-9ee9-4b68-a354-584ff8df6dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324428211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3324428211
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.3323474684
Short name T416
Test name
Test status
Simulation time 120812696298 ps
CPU time 203.81 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 09:33:22 AM PDT 24
Peak memory 191360 kb
Host smart-54ae8114-0604-4fcf-8923-301f1eb2d142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323474684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3323474684
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1412310325
Short name T175
Test name
Test status
Simulation time 559832001219 ps
CPU time 332.92 seconds
Started Jul 02 09:29:54 AM PDT 24
Finished Jul 02 09:35:28 AM PDT 24
Peak memory 191304 kb
Host smart-ac3a23a0-0433-422f-a8e5-97fbd1fc730f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412310325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1412310325
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2955821865
Short name T127
Test name
Test status
Simulation time 226171574172 ps
CPU time 207.56 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 09:33:26 AM PDT 24
Peak memory 191340 kb
Host smart-fab2f146-5b25-4bf1-8746-7b07c9828fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955821865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2955821865
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1806218393
Short name T305
Test name
Test status
Simulation time 571705902454 ps
CPU time 612.49 seconds
Started Jul 02 09:29:59 AM PDT 24
Finished Jul 02 09:40:12 AM PDT 24
Peak memory 191320 kb
Host smart-ef028473-a915-443f-be6f-de77d4a2b465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806218393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1806218393
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2472518623
Short name T291
Test name
Test status
Simulation time 38053307399 ps
CPU time 122.68 seconds
Started Jul 02 09:29:59 AM PDT 24
Finished Jul 02 09:32:02 AM PDT 24
Peak memory 191368 kb
Host smart-899577da-61a7-4df4-86d6-a800bb4eafc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472518623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2472518623
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.744917123
Short name T431
Test name
Test status
Simulation time 281707565368 ps
CPU time 194.01 seconds
Started Jul 02 09:28:10 AM PDT 24
Finished Jul 02 09:31:24 AM PDT 24
Peak memory 183152 kb
Host smart-d45b24ff-1371-480d-ba3b-7263e960640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744917123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.744917123
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.655860810
Short name T415
Test name
Test status
Simulation time 271298585623 ps
CPU time 217.56 seconds
Started Jul 02 09:28:09 AM PDT 24
Finished Jul 02 09:31:47 AM PDT 24
Peak memory 193552 kb
Host smart-e845096c-98af-4b35-a119-9c82350a42d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655860810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.655860810
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3644671892
Short name T220
Test name
Test status
Simulation time 30380208143 ps
CPU time 66.97 seconds
Started Jul 02 09:28:13 AM PDT 24
Finished Jul 02 09:29:20 AM PDT 24
Peak memory 191320 kb
Host smart-a8fc55b8-00ae-4245-805f-ed5efc3956d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644671892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3644671892
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1355983487
Short name T424
Test name
Test status
Simulation time 79849792348 ps
CPU time 105.85 seconds
Started Jul 02 09:28:11 AM PDT 24
Finished Jul 02 09:29:58 AM PDT 24
Peak memory 183132 kb
Host smart-94a8fc86-3b65-49e9-a78d-2ddb376b3718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355983487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1355983487
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.2939490667
Short name T277
Test name
Test status
Simulation time 396515597785 ps
CPU time 296.56 seconds
Started Jul 02 09:30:01 AM PDT 24
Finished Jul 02 09:34:58 AM PDT 24
Peak memory 191364 kb
Host smart-b03b0664-97a9-49f8-bb84-ad8cc19b7d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939490667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2939490667
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2941865952
Short name T242
Test name
Test status
Simulation time 110212722964 ps
CPU time 159.02 seconds
Started Jul 02 09:30:00 AM PDT 24
Finished Jul 02 09:32:40 AM PDT 24
Peak memory 191364 kb
Host smart-1efb0ad3-ec9c-4343-a166-390d9ddb3bb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941865952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2941865952
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1140356842
Short name T253
Test name
Test status
Simulation time 37321773177 ps
CPU time 63.31 seconds
Started Jul 02 09:29:58 AM PDT 24
Finished Jul 02 09:31:02 AM PDT 24
Peak memory 183148 kb
Host smart-e8516988-d0ca-44c1-a471-77eee0c3a0b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140356842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1140356842
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3581769737
Short name T112
Test name
Test status
Simulation time 91263204137 ps
CPU time 1058.05 seconds
Started Jul 02 09:30:02 AM PDT 24
Finished Jul 02 09:47:41 AM PDT 24
Peak memory 191360 kb
Host smart-4e9c6869-366c-428f-b5fd-ea05e99f7d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581769737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3581769737
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3772481315
Short name T211
Test name
Test status
Simulation time 150566831981 ps
CPU time 128.28 seconds
Started Jul 02 09:30:04 AM PDT 24
Finished Jul 02 09:32:12 AM PDT 24
Peak memory 191332 kb
Host smart-04257251-78b5-421b-92fc-0d26ad79c10b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772481315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3772481315
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2665070708
Short name T190
Test name
Test status
Simulation time 71042662372 ps
CPU time 135.11 seconds
Started Jul 02 09:30:05 AM PDT 24
Finished Jul 02 09:32:21 AM PDT 24
Peak memory 191352 kb
Host smart-16ca71b5-dc4d-40f1-a244-e6224f7e900b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665070708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2665070708
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.4266615149
Short name T430
Test name
Test status
Simulation time 445862194916 ps
CPU time 1043.13 seconds
Started Jul 02 09:30:02 AM PDT 24
Finished Jul 02 09:47:25 AM PDT 24
Peak memory 191360 kb
Host smart-211a4cc5-f68a-4da7-811b-cf6ef698b816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266615149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4266615149
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1631449600
Short name T167
Test name
Test status
Simulation time 109906953274 ps
CPU time 339.79 seconds
Started Jul 02 09:30:06 AM PDT 24
Finished Jul 02 09:35:46 AM PDT 24
Peak memory 191360 kb
Host smart-c7c3be40-dfc4-4421-85f6-b8783fa91bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631449600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1631449600
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1972304098
Short name T311
Test name
Test status
Simulation time 9586463298 ps
CPU time 14.15 seconds
Started Jul 02 09:28:11 AM PDT 24
Finished Jul 02 09:28:26 AM PDT 24
Peak memory 183140 kb
Host smart-d229f4eb-2767-4677-9285-604f566fb40d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972304098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1972304098
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3275818656
Short name T400
Test name
Test status
Simulation time 304767836252 ps
CPU time 229.88 seconds
Started Jul 02 09:28:10 AM PDT 24
Finished Jul 02 09:32:00 AM PDT 24
Peak memory 183188 kb
Host smart-dc60d0f0-152f-484b-be0b-820e552dea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275818656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3275818656
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2327596277
Short name T189
Test name
Test status
Simulation time 120659410979 ps
CPU time 924.42 seconds
Started Jul 02 09:28:09 AM PDT 24
Finished Jul 02 09:43:34 AM PDT 24
Peak memory 191360 kb
Host smart-2555566d-48d7-4f34-9b4a-4e87be89b2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327596277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2327596277
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1358361201
Short name T432
Test name
Test status
Simulation time 348001283093 ps
CPU time 162.18 seconds
Started Jul 02 09:28:11 AM PDT 24
Finished Jul 02 09:30:54 AM PDT 24
Peak memory 191340 kb
Host smart-fab2f6e8-ac72-4dbd-b465-d14a9de498ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358361201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1358361201
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.818626841
Short name T62
Test name
Test status
Simulation time 405604736445 ps
CPU time 567.35 seconds
Started Jul 02 09:28:11 AM PDT 24
Finished Jul 02 09:37:39 AM PDT 24
Peak memory 195824 kb
Host smart-3d37c06a-cc27-49e5-8b7f-7a5a309d2ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818626841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
818626841
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.4204659193
Short name T304
Test name
Test status
Simulation time 626151045187 ps
CPU time 329.88 seconds
Started Jul 02 09:30:10 AM PDT 24
Finished Jul 02 09:35:40 AM PDT 24
Peak memory 191360 kb
Host smart-3358e3a4-bdcb-4fc2-9db6-842eef8ffea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204659193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.4204659193
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3831278114
Short name T174
Test name
Test status
Simulation time 316706346066 ps
CPU time 159.88 seconds
Started Jul 02 09:30:06 AM PDT 24
Finished Jul 02 09:32:47 AM PDT 24
Peak memory 191348 kb
Host smart-1a20ccb3-d555-4aab-81bb-59363fca41c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831278114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3831278114
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1474610152
Short name T206
Test name
Test status
Simulation time 90735996905 ps
CPU time 77.41 seconds
Started Jul 02 09:30:07 AM PDT 24
Finished Jul 02 09:31:25 AM PDT 24
Peak memory 183140 kb
Host smart-6e28f8b3-633a-4d93-a22d-133b4c910f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474610152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1474610152
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3029882257
Short name T120
Test name
Test status
Simulation time 111782097017 ps
CPU time 212 seconds
Started Jul 02 09:30:07 AM PDT 24
Finished Jul 02 09:33:39 AM PDT 24
Peak memory 191272 kb
Host smart-c26a80e0-041f-4ffb-b416-5bc0d2fdde86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029882257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3029882257
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.760218673
Short name T147
Test name
Test status
Simulation time 338898121023 ps
CPU time 504.23 seconds
Started Jul 02 09:30:15 AM PDT 24
Finished Jul 02 09:38:40 AM PDT 24
Peak memory 191316 kb
Host smart-c8bdd890-996a-49a9-aa02-603e4a62a080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760218673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.760218673
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2635625255
Short name T272
Test name
Test status
Simulation time 122221044874 ps
CPU time 93.34 seconds
Started Jul 02 09:30:15 AM PDT 24
Finished Jul 02 09:31:48 AM PDT 24
Peak memory 191340 kb
Host smart-ed3e71b0-923b-4ada-a3da-6c07e5adce3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635625255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2635625255
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.643370100
Short name T116
Test name
Test status
Simulation time 99572019784 ps
CPU time 152.11 seconds
Started Jul 02 09:30:09 AM PDT 24
Finished Jul 02 09:32:41 AM PDT 24
Peak memory 191356 kb
Host smart-eb52c4dc-62f6-4074-b5df-d9c2c82f9890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643370100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.643370100
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1180977684
Short name T397
Test name
Test status
Simulation time 35532797622 ps
CPU time 11.7 seconds
Started Jul 02 09:28:14 AM PDT 24
Finished Jul 02 09:28:26 AM PDT 24
Peak memory 183132 kb
Host smart-5d0ac55e-c468-44e1-828e-1daba61488c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180977684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1180977684
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1362227385
Short name T378
Test name
Test status
Simulation time 149834289444 ps
CPU time 187.53 seconds
Started Jul 02 09:28:16 AM PDT 24
Finished Jul 02 09:31:25 AM PDT 24
Peak memory 183176 kb
Host smart-dfdf168a-3f92-46ea-86e6-291f4f691830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362227385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1362227385
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1732213114
Short name T338
Test name
Test status
Simulation time 556524329078 ps
CPU time 582.29 seconds
Started Jul 02 09:28:13 AM PDT 24
Finished Jul 02 09:37:56 AM PDT 24
Peak memory 194424 kb
Host smart-b7f59425-a9d2-4363-ae58-350ad769101d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732213114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1732213114
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3233540755
Short name T331
Test name
Test status
Simulation time 75635716870 ps
CPU time 151.31 seconds
Started Jul 02 09:28:17 AM PDT 24
Finished Jul 02 09:30:49 AM PDT 24
Peak memory 183192 kb
Host smart-eb056aed-f302-456f-8afe-a9cc2b51b8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233540755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3233540755
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.3338618065
Short name T414
Test name
Test status
Simulation time 70776133958 ps
CPU time 56.22 seconds
Started Jul 02 09:30:10 AM PDT 24
Finished Jul 02 09:31:06 AM PDT 24
Peak memory 183128 kb
Host smart-6cc3acbe-5889-4831-b651-303d3dd6816b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338618065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3338618065
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2623122621
Short name T310
Test name
Test status
Simulation time 1334516388 ps
CPU time 27.08 seconds
Started Jul 02 09:30:16 AM PDT 24
Finished Jul 02 09:30:44 AM PDT 24
Peak memory 183104 kb
Host smart-40e293ab-76d6-44a1-8b7d-5227e244f346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623122621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2623122621
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1903203708
Short name T275
Test name
Test status
Simulation time 118535240469 ps
CPU time 957.35 seconds
Started Jul 02 09:30:15 AM PDT 24
Finished Jul 02 09:46:13 AM PDT 24
Peak memory 191368 kb
Host smart-c203fbb6-4c15-4af4-bf7a-ad8a87f5c1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903203708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1903203708
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2425698684
Short name T231
Test name
Test status
Simulation time 44440763128 ps
CPU time 98.64 seconds
Started Jul 02 09:30:16 AM PDT 24
Finished Jul 02 09:31:55 AM PDT 24
Peak memory 191376 kb
Host smart-0055a831-eebb-41bb-b597-2e9f2a5e0107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425698684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2425698684
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.539734268
Short name T328
Test name
Test status
Simulation time 216663859816 ps
CPU time 116.22 seconds
Started Jul 02 09:30:16 AM PDT 24
Finished Jul 02 09:32:13 AM PDT 24
Peak memory 191368 kb
Host smart-2e8ac766-4d63-45c3-abe0-53dffc0f0966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539734268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.539734268
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3715581922
Short name T178
Test name
Test status
Simulation time 61421109948 ps
CPU time 142.01 seconds
Started Jul 02 09:30:16 AM PDT 24
Finished Jul 02 09:32:39 AM PDT 24
Peak memory 183136 kb
Host smart-36fa882d-f6ac-444c-9db7-5e4a8b8a5fa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715581922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3715581922
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2974109122
Short name T157
Test name
Test status
Simulation time 127004259478 ps
CPU time 958.37 seconds
Started Jul 02 09:30:15 AM PDT 24
Finished Jul 02 09:46:14 AM PDT 24
Peak memory 191320 kb
Host smart-62ad3581-0891-4bb2-b79a-b226ad154351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974109122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2974109122
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.718833828
Short name T332
Test name
Test status
Simulation time 273891960173 ps
CPU time 417.8 seconds
Started Jul 02 09:30:16 AM PDT 24
Finished Jul 02 09:37:14 AM PDT 24
Peak memory 191372 kb
Host smart-22c55549-303f-49fa-8063-a074a2a5480f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718833828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.718833828
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.76195618
Short name T281
Test name
Test status
Simulation time 683543943510 ps
CPU time 630.68 seconds
Started Jul 02 09:28:15 AM PDT 24
Finished Jul 02 09:38:47 AM PDT 24
Peak memory 183172 kb
Host smart-c7c1a0e1-a2a0-41c3-8013-88b6791ac40f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76195618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.rv_timer_cfg_update_on_fly.76195618
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.996731253
Short name T368
Test name
Test status
Simulation time 329970244001 ps
CPU time 132.34 seconds
Started Jul 02 09:28:14 AM PDT 24
Finished Jul 02 09:30:26 AM PDT 24
Peak memory 183180 kb
Host smart-fa5d5153-b75d-421e-b5fa-787dd23a15db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996731253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.996731253
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1672190574
Short name T225
Test name
Test status
Simulation time 159230670678 ps
CPU time 168.6 seconds
Started Jul 02 09:28:15 AM PDT 24
Finished Jul 02 09:31:05 AM PDT 24
Peak memory 191300 kb
Host smart-d38f49a7-05e6-4ad9-ae55-3d861f7d7f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672190574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1672190574
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.345950247
Short name T26
Test name
Test status
Simulation time 14764335480 ps
CPU time 35.51 seconds
Started Jul 02 09:28:16 AM PDT 24
Finished Jul 02 09:28:53 AM PDT 24
Peak memory 191360 kb
Host smart-6ff70957-657f-408a-9f7a-9bb2accbecfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345950247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.345950247
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.1876030524
Short name T219
Test name
Test status
Simulation time 196465485424 ps
CPU time 62.19 seconds
Started Jul 02 09:30:18 AM PDT 24
Finished Jul 02 09:31:21 AM PDT 24
Peak memory 183020 kb
Host smart-598ab5d9-8bee-456d-84d4-5e65729513e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876030524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1876030524
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2385003566
Short name T236
Test name
Test status
Simulation time 140674482193 ps
CPU time 1863.33 seconds
Started Jul 02 09:30:19 AM PDT 24
Finished Jul 02 10:01:22 AM PDT 24
Peak memory 191272 kb
Host smart-62ac64f9-00c2-4385-b85e-d783e9121097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385003566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2385003566
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3231668191
Short name T151
Test name
Test status
Simulation time 161163103725 ps
CPU time 492.72 seconds
Started Jul 02 09:30:25 AM PDT 24
Finished Jul 02 09:38:38 AM PDT 24
Peak memory 191352 kb
Host smart-8eb02a0b-03df-469e-adc9-32baad8dcafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231668191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3231668191
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2029207264
Short name T248
Test name
Test status
Simulation time 130129975782 ps
CPU time 245.75 seconds
Started Jul 02 09:30:23 AM PDT 24
Finished Jul 02 09:34:29 AM PDT 24
Peak memory 191332 kb
Host smart-ab173e72-1789-4cce-b3f1-389ec9c16a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029207264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2029207264
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2512271995
Short name T353
Test name
Test status
Simulation time 255364769741 ps
CPU time 801.73 seconds
Started Jul 02 09:30:22 AM PDT 24
Finished Jul 02 09:43:44 AM PDT 24
Peak memory 191300 kb
Host smart-179d7e26-3be6-44d4-b026-55dce8c62996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512271995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2512271995
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2685419816
Short name T402
Test name
Test status
Simulation time 49845662590 ps
CPU time 43.67 seconds
Started Jul 02 09:30:26 AM PDT 24
Finished Jul 02 09:31:10 AM PDT 24
Peak memory 183168 kb
Host smart-25ce3cf0-7389-4685-8f1f-766bf5d3e7c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685419816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2685419816
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.122424128
Short name T436
Test name
Test status
Simulation time 38927541739 ps
CPU time 65.36 seconds
Started Jul 02 09:28:18 AM PDT 24
Finished Jul 02 09:29:24 AM PDT 24
Peak memory 183112 kb
Host smart-3739df82-e043-41f2-b529-fe6e76c8e384
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122424128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.122424128
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1437191837
Short name T407
Test name
Test status
Simulation time 53872742488 ps
CPU time 68.33 seconds
Started Jul 02 09:28:16 AM PDT 24
Finished Jul 02 09:29:25 AM PDT 24
Peak memory 183156 kb
Host smart-c9d0d121-ad26-4df3-80a3-a0db34ac56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437191837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1437191837
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2062808141
Short name T6
Test name
Test status
Simulation time 80452049317 ps
CPU time 39.52 seconds
Started Jul 02 09:28:17 AM PDT 24
Finished Jul 02 09:28:57 AM PDT 24
Peak memory 191336 kb
Host smart-e587cfd4-0dc8-4fbf-9c5f-e40fc6c1d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062808141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2062808141
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3073256676
Short name T34
Test name
Test status
Simulation time 512380395821 ps
CPU time 756.64 seconds
Started Jul 02 09:28:16 AM PDT 24
Finished Jul 02 09:40:54 AM PDT 24
Peak memory 191360 kb
Host smart-9ab6c913-ffc3-425a-8f40-2f16e34977bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073256676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3073256676
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.87210360
Short name T410
Test name
Test status
Simulation time 14843013365 ps
CPU time 258.85 seconds
Started Jul 02 09:30:25 AM PDT 24
Finished Jul 02 09:34:44 AM PDT 24
Peak memory 183096 kb
Host smart-8636526b-e20a-4358-9d01-aa2012896e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87210360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.87210360
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.614479591
Short name T330
Test name
Test status
Simulation time 456133664732 ps
CPU time 211.48 seconds
Started Jul 02 09:30:26 AM PDT 24
Finished Jul 02 09:33:57 AM PDT 24
Peak memory 191380 kb
Host smart-39cbc274-d93f-483a-8a3d-f827719f9c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614479591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.614479591
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.627938239
Short name T268
Test name
Test status
Simulation time 16790148031 ps
CPU time 14.19 seconds
Started Jul 02 09:30:28 AM PDT 24
Finished Jul 02 09:30:43 AM PDT 24
Peak memory 183172 kb
Host smart-9cbb2d21-eece-447f-a703-6afe7fe56356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627938239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.627938239
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2034881602
Short name T297
Test name
Test status
Simulation time 75244657957 ps
CPU time 86.26 seconds
Started Jul 02 09:30:31 AM PDT 24
Finished Jul 02 09:31:58 AM PDT 24
Peak memory 191336 kb
Host smart-37f479c6-8d2b-46fa-b30f-04721f827877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034881602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2034881602
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2829431517
Short name T156
Test name
Test status
Simulation time 119266144595 ps
CPU time 210.47 seconds
Started Jul 02 09:30:34 AM PDT 24
Finished Jul 02 09:34:05 AM PDT 24
Peak memory 191348 kb
Host smart-18b3aac6-415f-4a4e-b15e-46a2fcab334a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829431517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2829431517
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2158356404
Short name T336
Test name
Test status
Simulation time 267448406563 ps
CPU time 2189.59 seconds
Started Jul 02 09:30:31 AM PDT 24
Finished Jul 02 10:07:01 AM PDT 24
Peak memory 191336 kb
Host smart-fbe51ead-90d1-4f35-966f-1bd031ec655f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158356404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2158356404
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2976761886
Short name T4
Test name
Test status
Simulation time 30289786495 ps
CPU time 44.41 seconds
Started Jul 02 09:30:34 AM PDT 24
Finished Jul 02 09:31:19 AM PDT 24
Peak memory 183148 kb
Host smart-c667d81f-e20c-46df-ac29-aa181bf9414d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976761886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2976761886
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1606823069
Short name T249
Test name
Test status
Simulation time 145915504096 ps
CPU time 798.85 seconds
Started Jul 02 09:30:32 AM PDT 24
Finished Jul 02 09:43:51 AM PDT 24
Peak memory 191360 kb
Host smart-0d169c1c-826a-4904-aaa7-aff49a4cf94a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606823069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1606823069
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1442145629
Short name T133
Test name
Test status
Simulation time 577613744499 ps
CPU time 560.58 seconds
Started Jul 02 09:30:37 AM PDT 24
Finished Jul 02 09:39:58 AM PDT 24
Peak memory 191348 kb
Host smart-765a81e9-6cab-4cf8-9893-322b33dfe6dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442145629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1442145629
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1670995031
Short name T200
Test name
Test status
Simulation time 119645983806 ps
CPU time 201.54 seconds
Started Jul 02 09:28:17 AM PDT 24
Finished Jul 02 09:31:40 AM PDT 24
Peak memory 183128 kb
Host smart-dcd2f5b0-9180-4e7c-9d3c-02eabb842666
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670995031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1670995031
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.577562883
Short name T367
Test name
Test status
Simulation time 31450117964 ps
CPU time 41.13 seconds
Started Jul 02 09:28:16 AM PDT 24
Finished Jul 02 09:28:58 AM PDT 24
Peak memory 183148 kb
Host smart-5aa62b8e-4e67-4940-9468-0582414042d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577562883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.577562883
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2941830876
Short name T195
Test name
Test status
Simulation time 411375960459 ps
CPU time 257.29 seconds
Started Jul 02 09:28:15 AM PDT 24
Finished Jul 02 09:32:34 AM PDT 24
Peak memory 191364 kb
Host smart-2cd38f6b-cd1a-4a03-8b82-95068927599b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941830876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2941830876
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.682702483
Short name T322
Test name
Test status
Simulation time 85832598849 ps
CPU time 98.83 seconds
Started Jul 02 09:28:15 AM PDT 24
Finished Jul 02 09:29:54 AM PDT 24
Peak memory 191336 kb
Host smart-47ec3af5-9c40-4a45-aa1c-77e59aae884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682702483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.682702483
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.604178115
Short name T58
Test name
Test status
Simulation time 211303575983 ps
CPU time 219.9 seconds
Started Jul 02 09:28:17 AM PDT 24
Finished Jul 02 09:31:58 AM PDT 24
Peak memory 195728 kb
Host smart-56b6666e-dba4-4f68-8e0a-dc6797bf7017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604178115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
604178115
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.581002131
Short name T13
Test name
Test status
Simulation time 36195684364 ps
CPU time 192.77 seconds
Started Jul 02 09:28:18 AM PDT 24
Finished Jul 02 09:31:32 AM PDT 24
Peak memory 197844 kb
Host smart-57edf8cf-ee5b-4340-9c9d-beb85ecf989b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581002131 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.581002131
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2954373462
Short name T27
Test name
Test status
Simulation time 29035916492 ps
CPU time 51.13 seconds
Started Jul 02 09:30:36 AM PDT 24
Finished Jul 02 09:31:28 AM PDT 24
Peak memory 191340 kb
Host smart-c9e179d8-e5be-40da-ac3c-7b37dc90d92e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954373462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2954373462
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2357170542
Short name T339
Test name
Test status
Simulation time 29471985339 ps
CPU time 50.59 seconds
Started Jul 02 09:30:36 AM PDT 24
Finished Jul 02 09:31:26 AM PDT 24
Peak memory 191356 kb
Host smart-39be47d7-bd90-4118-bd83-098cbdde3b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357170542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2357170542
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1479380838
Short name T199
Test name
Test status
Simulation time 1832059933472 ps
CPU time 994.49 seconds
Started Jul 02 09:30:35 AM PDT 24
Finished Jul 02 09:47:10 AM PDT 24
Peak memory 191388 kb
Host smart-1de3ffd2-9b44-4f57-a960-64d8196bc8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479380838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1479380838
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1592363569
Short name T320
Test name
Test status
Simulation time 67709161415 ps
CPU time 116.69 seconds
Started Jul 02 09:30:40 AM PDT 24
Finished Jul 02 09:32:37 AM PDT 24
Peak memory 191360 kb
Host smart-a0e3575d-a3e6-4776-b56f-3332ba2ca672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592363569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1592363569
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2381164127
Short name T25
Test name
Test status
Simulation time 47349159303 ps
CPU time 254.1 seconds
Started Jul 02 09:30:40 AM PDT 24
Finished Jul 02 09:34:54 AM PDT 24
Peak memory 191352 kb
Host smart-8cc0d43d-e118-400e-837e-52fee18e5b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381164127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2381164127
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.456384999
Short name T441
Test name
Test status
Simulation time 30746763103 ps
CPU time 52.7 seconds
Started Jul 02 09:30:43 AM PDT 24
Finished Jul 02 09:31:36 AM PDT 24
Peak memory 183164 kb
Host smart-2b955053-7ee9-46a1-9c77-8eaa340561ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456384999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.456384999
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3429333647
Short name T64
Test name
Test status
Simulation time 129590488927 ps
CPU time 114.69 seconds
Started Jul 02 09:30:44 AM PDT 24
Finished Jul 02 09:32:39 AM PDT 24
Peak memory 191376 kb
Host smart-3951db98-932a-412f-a100-5b738a508d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429333647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3429333647
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3454393583
Short name T323
Test name
Test status
Simulation time 119595751657 ps
CPU time 53.6 seconds
Started Jul 02 09:30:47 AM PDT 24
Finished Jul 02 09:31:41 AM PDT 24
Peak memory 183148 kb
Host smart-3828a126-0922-4a21-b270-8f686d265c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454393583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3454393583
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1677841308
Short name T66
Test name
Test status
Simulation time 44055683057 ps
CPU time 70.51 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:29:14 AM PDT 24
Peak memory 183160 kb
Host smart-95e1ca96-2ec8-4602-859f-b4bbf9776f53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677841308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1677841308
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2085737430
Short name T71
Test name
Test status
Simulation time 96723372787 ps
CPU time 134.57 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:30:13 AM PDT 24
Peak memory 183160 kb
Host smart-5a223806-aae4-4ae2-86b6-65504dd67311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085737430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2085737430
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.409633076
Short name T308
Test name
Test status
Simulation time 78426907675 ps
CPU time 79.8 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:29:19 AM PDT 24
Peak memory 191332 kb
Host smart-5c204886-8c7b-40f0-b9de-d266045da0a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409633076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.409633076
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1962363675
Short name T296
Test name
Test status
Simulation time 114897368157 ps
CPU time 207.96 seconds
Started Jul 02 09:27:57 AM PDT 24
Finished Jul 02 09:31:25 AM PDT 24
Peak memory 191524 kb
Host smart-e635cc0b-cff1-4d9a-8d57-2e15ba5e95be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962363675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1962363675
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2168723484
Short name T17
Test name
Test status
Simulation time 1063592415 ps
CPU time 0.94 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:28:04 AM PDT 24
Peak memory 214456 kb
Host smart-86a9a728-4c64-4e21-8230-893ab959d87e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168723484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2168723484
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1184589633
Short name T376
Test name
Test status
Simulation time 1003753329465 ps
CPU time 161.31 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:30:40 AM PDT 24
Peak memory 191348 kb
Host smart-650641f0-3e5e-4f57-9953-b1d0bda5d4d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184589633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1184589633
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1055121192
Short name T299
Test name
Test status
Simulation time 236674089819 ps
CPU time 206.38 seconds
Started Jul 02 09:28:15 AM PDT 24
Finished Jul 02 09:31:42 AM PDT 24
Peak memory 183152 kb
Host smart-8e9fcd47-b40a-4d07-a7df-ccf85a16bcc2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055121192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1055121192
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1860865670
Short name T390
Test name
Test status
Simulation time 63701060582 ps
CPU time 86.85 seconds
Started Jul 02 09:28:14 AM PDT 24
Finished Jul 02 09:29:41 AM PDT 24
Peak memory 183092 kb
Host smart-271aa007-a5cd-4866-bba2-f3f2c30add5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860865670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1860865670
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.40481280
Short name T213
Test name
Test status
Simulation time 189682313212 ps
CPU time 547.45 seconds
Started Jul 02 09:28:12 AM PDT 24
Finished Jul 02 09:37:20 AM PDT 24
Peak memory 191332 kb
Host smart-521394ad-47c8-427e-87b8-b9bcf7d6e9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40481280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.40481280
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2504907177
Short name T19
Test name
Test status
Simulation time 857671254 ps
CPU time 1.28 seconds
Started Jul 02 09:28:18 AM PDT 24
Finished Jul 02 09:28:20 AM PDT 24
Peak memory 191336 kb
Host smart-ca9655df-08b5-47db-954f-d32da51e8151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504907177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2504907177
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.818235314
Short name T355
Test name
Test status
Simulation time 358283650687 ps
CPU time 90.65 seconds
Started Jul 02 09:28:18 AM PDT 24
Finished Jul 02 09:29:49 AM PDT 24
Peak memory 183160 kb
Host smart-4ee4ad10-e814-4dc4-b6a6-d48698684313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818235314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.818235314
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.981601004
Short name T181
Test name
Test status
Simulation time 206155565807 ps
CPU time 135.66 seconds
Started Jul 02 09:28:22 AM PDT 24
Finished Jul 02 09:30:38 AM PDT 24
Peak memory 191376 kb
Host smart-57a7985b-db9c-48f5-9904-a26ec469df85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981601004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.981601004
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3235557272
Short name T411
Test name
Test status
Simulation time 16866585751 ps
CPU time 8.48 seconds
Started Jul 02 09:28:20 AM PDT 24
Finished Jul 02 09:28:29 AM PDT 24
Peak memory 195236 kb
Host smart-e0452316-45c9-4153-9a3d-090610cece09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235557272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3235557272
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.4244069160
Short name T443
Test name
Test status
Simulation time 156224541025 ps
CPU time 195.15 seconds
Started Jul 02 09:28:18 AM PDT 24
Finished Jul 02 09:31:34 AM PDT 24
Peak memory 183136 kb
Host smart-f85f83fe-825c-4340-b2f2-764fd5809ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244069160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.4244069160
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1806739761
Short name T361
Test name
Test status
Simulation time 40949962 ps
CPU time 0.56 seconds
Started Jul 02 09:28:24 AM PDT 24
Finished Jul 02 09:28:25 AM PDT 24
Peak memory 182672 kb
Host smart-1d3bb8af-32bf-448d-84ff-8e4432271377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806739761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1806739761
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2105404134
Short name T335
Test name
Test status
Simulation time 1472697909166 ps
CPU time 778.14 seconds
Started Jul 02 09:28:16 AM PDT 24
Finished Jul 02 09:41:16 AM PDT 24
Peak memory 191368 kb
Host smart-ee7b3b26-12a6-414d-9fa6-a27d26bccbd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105404134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2105404134
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2400852173
Short name T162
Test name
Test status
Simulation time 461905333193 ps
CPU time 399.98 seconds
Started Jul 02 09:28:18 AM PDT 24
Finished Jul 02 09:34:59 AM PDT 24
Peak memory 183092 kb
Host smart-753bb19a-907e-421e-8b3a-29967364c4df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400852173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2400852173
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2444933035
Short name T362
Test name
Test status
Simulation time 176512656023 ps
CPU time 271.06 seconds
Started Jul 02 09:28:18 AM PDT 24
Finished Jul 02 09:32:50 AM PDT 24
Peak memory 183168 kb
Host smart-3182d8e7-7237-4db8-9111-e2b4cb324aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444933035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2444933035
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1761220189
Short name T307
Test name
Test status
Simulation time 280591535772 ps
CPU time 264.88 seconds
Started Jul 02 09:28:24 AM PDT 24
Finished Jul 02 09:32:50 AM PDT 24
Peak memory 191028 kb
Host smart-0168488f-9917-4eac-9f1d-a00cde244b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761220189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1761220189
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3690723787
Short name T380
Test name
Test status
Simulation time 849731051 ps
CPU time 1.19 seconds
Started Jul 02 09:28:17 AM PDT 24
Finished Jul 02 09:28:20 AM PDT 24
Peak memory 183028 kb
Host smart-f420ba48-dc26-4970-b52d-8a84822e2562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690723787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3690723787
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2498644301
Short name T122
Test name
Test status
Simulation time 868510653986 ps
CPU time 565.14 seconds
Started Jul 02 09:28:18 AM PDT 24
Finished Jul 02 09:37:44 AM PDT 24
Peak memory 191300 kb
Host smart-19505699-8573-444c-88a4-15e08a89e5c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498644301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2498644301
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2629014809
Short name T38
Test name
Test status
Simulation time 86406665484 ps
CPU time 238.04 seconds
Started Jul 02 09:28:23 AM PDT 24
Finished Jul 02 09:32:22 AM PDT 24
Peak memory 206024 kb
Host smart-c01d9ad4-65b3-4a18-a446-3c249f57f75c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629014809 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2629014809
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.974557776
Short name T429
Test name
Test status
Simulation time 359206781807 ps
CPU time 136.88 seconds
Started Jul 02 09:28:24 AM PDT 24
Finished Jul 02 09:30:42 AM PDT 24
Peak memory 183124 kb
Host smart-499e0c0d-4724-4934-93ff-7d0ec134df53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974557776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.974557776
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2815116310
Short name T65
Test name
Test status
Simulation time 78161620480 ps
CPU time 135.66 seconds
Started Jul 02 09:28:20 AM PDT 24
Finished Jul 02 09:30:36 AM PDT 24
Peak memory 191380 kb
Host smart-0f3cc7e1-e666-45ec-b61f-f6d867846838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815116310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2815116310
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2955120575
Short name T426
Test name
Test status
Simulation time 143292998625 ps
CPU time 139.74 seconds
Started Jul 02 09:28:23 AM PDT 24
Finished Jul 02 09:30:44 AM PDT 24
Peak memory 191324 kb
Host smart-b54f5569-dd38-4524-8e7f-5b95f104e70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955120575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2955120575
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1379813873
Short name T11
Test name
Test status
Simulation time 483825177080 ps
CPU time 780.17 seconds
Started Jul 02 09:28:28 AM PDT 24
Finished Jul 02 09:41:29 AM PDT 24
Peak memory 208712 kb
Host smart-1e9fd4f8-418d-482b-8b2e-44d77e4e0ae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379813873 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1379813873
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1463730091
Short name T173
Test name
Test status
Simulation time 153580829501 ps
CPU time 128.75 seconds
Started Jul 02 09:28:23 AM PDT 24
Finished Jul 02 09:30:32 AM PDT 24
Peak memory 183124 kb
Host smart-59f74ee7-b349-4082-b7e0-b09ba0eeadb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463730091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1463730091
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1095764722
Short name T375
Test name
Test status
Simulation time 250967252724 ps
CPU time 162.21 seconds
Started Jul 02 09:28:22 AM PDT 24
Finished Jul 02 09:31:05 AM PDT 24
Peak memory 183092 kb
Host smart-26f3fdc2-7e0a-46e0-9509-a4263d1805c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095764722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1095764722
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.235893510
Short name T433
Test name
Test status
Simulation time 25349308775 ps
CPU time 41.06 seconds
Started Jul 02 09:28:23 AM PDT 24
Finished Jul 02 09:29:04 AM PDT 24
Peak memory 183152 kb
Host smart-6b419ccc-6333-45bc-ad8b-dfe40200fcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235893510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.235893510
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1091221033
Short name T366
Test name
Test status
Simulation time 594335023226 ps
CPU time 202.09 seconds
Started Jul 02 09:28:31 AM PDT 24
Finished Jul 02 09:31:55 AM PDT 24
Peak memory 183180 kb
Host smart-9170d6f9-5540-495e-8517-267038e4a36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091221033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1091221033
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.101820288
Short name T114
Test name
Test status
Simulation time 259250910081 ps
CPU time 129.09 seconds
Started Jul 02 09:28:24 AM PDT 24
Finished Jul 02 09:30:34 AM PDT 24
Peak memory 191316 kb
Host smart-8fe4ffbe-80bb-4356-9b49-268f00d7efb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101820288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.101820288
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3130235806
Short name T48
Test name
Test status
Simulation time 315034819608 ps
CPU time 430.27 seconds
Started Jul 02 09:28:22 AM PDT 24
Finished Jul 02 09:35:33 AM PDT 24
Peak memory 191332 kb
Host smart-6b12dfb4-d579-45da-9175-d253a8878f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130235806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3130235806
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.4020837037
Short name T444
Test name
Test status
Simulation time 186161219797 ps
CPU time 280.25 seconds
Started Jul 02 09:28:21 AM PDT 24
Finished Jul 02 09:33:02 AM PDT 24
Peak memory 183140 kb
Host smart-da0ae949-ec50-42f8-b832-68afe1b7d023
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020837037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.4020837037
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2096288303
Short name T363
Test name
Test status
Simulation time 448616476956 ps
CPU time 199.07 seconds
Started Jul 02 09:28:32 AM PDT 24
Finished Jul 02 09:31:52 AM PDT 24
Peak memory 183180 kb
Host smart-dffb50a7-a28b-46fe-84f2-1382a210aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096288303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2096288303
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3714904349
Short name T288
Test name
Test status
Simulation time 245947151998 ps
CPU time 626.98 seconds
Started Jul 02 09:28:20 AM PDT 24
Finished Jul 02 09:38:48 AM PDT 24
Peak memory 191380 kb
Host smart-401df995-22f8-4a4b-825f-1c476b123fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714904349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3714904349
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2855069460
Short name T276
Test name
Test status
Simulation time 46100579882 ps
CPU time 34.13 seconds
Started Jul 02 09:28:23 AM PDT 24
Finished Jul 02 09:28:58 AM PDT 24
Peak memory 191316 kb
Host smart-218254c1-4c35-4995-b067-32a22ae47f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855069460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2855069460
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2992333148
Short name T229
Test name
Test status
Simulation time 580646604862 ps
CPU time 281.32 seconds
Started Jul 02 09:28:31 AM PDT 24
Finished Jul 02 09:33:14 AM PDT 24
Peak memory 183148 kb
Host smart-69ceae8d-2340-4ab9-aef3-023bfc665481
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992333148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2992333148
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2445571721
Short name T46
Test name
Test status
Simulation time 116119764052 ps
CPU time 49.16 seconds
Started Jul 02 09:28:27 AM PDT 24
Finished Jul 02 09:29:17 AM PDT 24
Peak memory 183188 kb
Host smart-6e794b82-6bed-49fa-a3c3-586893add6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445571721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2445571721
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.232042282
Short name T309
Test name
Test status
Simulation time 359488235491 ps
CPU time 317.64 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 09:33:45 AM PDT 24
Peak memory 191324 kb
Host smart-daffedee-63db-432c-a31f-9e47f61b8dcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232042282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.232042282
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2280625722
Short name T159
Test name
Test status
Simulation time 42585277634 ps
CPU time 42.8 seconds
Started Jul 02 09:28:27 AM PDT 24
Finished Jul 02 09:29:11 AM PDT 24
Peak memory 191336 kb
Host smart-5a88d591-b622-4533-937d-9a50a00ea64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280625722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2280625722
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3788047289
Short name T187
Test name
Test status
Simulation time 140966834691 ps
CPU time 234.54 seconds
Started Jul 02 09:28:29 AM PDT 24
Finished Jul 02 09:32:24 AM PDT 24
Peak memory 183132 kb
Host smart-675ef9bb-432d-40e0-b7be-e39b0eed4220
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788047289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3788047289
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.338577041
Short name T440
Test name
Test status
Simulation time 64476544352 ps
CPU time 100.02 seconds
Started Jul 02 09:28:29 AM PDT 24
Finished Jul 02 09:30:10 AM PDT 24
Peak memory 183160 kb
Host smart-c3fa1ffb-f1db-44e7-a20f-bd138fac918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338577041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.338577041
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1611187493
Short name T266
Test name
Test status
Simulation time 283228313193 ps
CPU time 281.55 seconds
Started Jul 02 09:28:28 AM PDT 24
Finished Jul 02 09:33:11 AM PDT 24
Peak memory 191316 kb
Host smart-46f2cc99-5e8a-486e-9fd9-5245e4c98575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611187493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1611187493
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3153197728
Short name T343
Test name
Test status
Simulation time 257886829845 ps
CPU time 555.84 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 09:37:43 AM PDT 24
Peak memory 183096 kb
Host smart-15675895-16fc-4686-999b-657e5d92a464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153197728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3153197728
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2723626008
Short name T67
Test name
Test status
Simulation time 227472893764 ps
CPU time 125.19 seconds
Started Jul 02 09:27:58 AM PDT 24
Finished Jul 02 09:30:04 AM PDT 24
Peak memory 183176 kb
Host smart-ad53295b-596f-46f2-8bd6-6b6b9110b295
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723626008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2723626008
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2002485580
Short name T389
Test name
Test status
Simulation time 41286844654 ps
CPU time 62.03 seconds
Started Jul 02 09:27:59 AM PDT 24
Finished Jul 02 09:29:01 AM PDT 24
Peak memory 183116 kb
Host smart-64f9ac2d-6001-445c-9a75-fade4791bb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002485580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2002485580
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1383284846
Short name T227
Test name
Test status
Simulation time 837564259484 ps
CPU time 1167.86 seconds
Started Jul 02 09:28:00 AM PDT 24
Finished Jul 02 09:47:29 AM PDT 24
Peak memory 191320 kb
Host smart-2b38211c-cf79-4dd3-bbde-f8e06095168b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383284846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1383284846
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3962451269
Short name T250
Test name
Test status
Simulation time 598301419204 ps
CPU time 315.3 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:33:18 AM PDT 24
Peak memory 183188 kb
Host smart-3ac972f7-3c0e-4ac1-9423-3467f43b0467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962451269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3962451269
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3409204352
Short name T16
Test name
Test status
Simulation time 120047824 ps
CPU time 0.88 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:28:03 AM PDT 24
Peak memory 213484 kb
Host smart-cb2e67b8-35b9-4514-836c-75147563c201
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409204352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3409204352
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3370856829
Short name T60
Test name
Test status
Simulation time 369792629539 ps
CPU time 318.46 seconds
Started Jul 02 09:28:04 AM PDT 24
Finished Jul 02 09:33:23 AM PDT 24
Peak memory 196080 kb
Host smart-75067bdd-89ba-4d03-ba48-91f064472df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370856829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3370856829
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4275227395
Short name T262
Test name
Test status
Simulation time 720019529327 ps
CPU time 382.15 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 09:34:49 AM PDT 24
Peak memory 183152 kb
Host smart-a5c4d75a-90e6-40fe-ab3b-bf5a00542ed7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275227395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.4275227395
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2248884318
Short name T386
Test name
Test status
Simulation time 612915948804 ps
CPU time 165.52 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 09:31:13 AM PDT 24
Peak memory 183204 kb
Host smart-18693b7f-5435-4fb1-896d-108e3ffbd183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248884318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2248884318
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.984543124
Short name T312
Test name
Test status
Simulation time 175447815199 ps
CPU time 71.16 seconds
Started Jul 02 09:28:28 AM PDT 24
Finished Jul 02 09:29:40 AM PDT 24
Peak memory 195040 kb
Host smart-cc47c01d-a6b8-49d3-a41a-c603bf186c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984543124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.984543124
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1596105702
Short name T302
Test name
Test status
Simulation time 2380694918560 ps
CPU time 1082.24 seconds
Started Jul 02 09:28:33 AM PDT 24
Finished Jul 02 09:46:36 AM PDT 24
Peak memory 193772 kb
Host smart-cb763d72-9bfa-4e19-91a7-b17659b22166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596105702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1596105702
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2957440402
Short name T224
Test name
Test status
Simulation time 1112409217 ps
CPU time 1.06 seconds
Started Jul 02 09:28:30 AM PDT 24
Finished Jul 02 09:28:31 AM PDT 24
Peak memory 183004 kb
Host smart-d8c9e9f4-86ca-486f-a1eb-d2b43ee94572
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957440402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2957440402
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.663767140
Short name T434
Test name
Test status
Simulation time 491216832827 ps
CPU time 205.87 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 09:31:53 AM PDT 24
Peak memory 183132 kb
Host smart-7d090a22-47b2-464c-be65-f89f813b463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663767140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.663767140
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1387365776
Short name T194
Test name
Test status
Simulation time 760625512846 ps
CPU time 429.63 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 09:35:37 AM PDT 24
Peak memory 191356 kb
Host smart-f79579cc-d4cc-4dd2-9146-0e0d6751965d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387365776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1387365776
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2347562902
Short name T168
Test name
Test status
Simulation time 1722603647346 ps
CPU time 872.17 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 09:43:00 AM PDT 24
Peak memory 183132 kb
Host smart-35f2cc1e-b42b-4a34-921a-e82ab0ae345e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347562902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2347562902
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3060804726
Short name T379
Test name
Test status
Simulation time 87905352845 ps
CPU time 136.75 seconds
Started Jul 02 09:28:25 AM PDT 24
Finished Jul 02 09:30:43 AM PDT 24
Peak memory 183148 kb
Host smart-26e294ec-79f9-4f88-8deb-bd2e5cb4baee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060804726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3060804726
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2865009097
Short name T395
Test name
Test status
Simulation time 34747625689 ps
CPU time 48.07 seconds
Started Jul 02 09:28:30 AM PDT 24
Finished Jul 02 09:29:18 AM PDT 24
Peak memory 183096 kb
Host smart-170cb325-382b-4771-bd4c-ffdc16995cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865009097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2865009097
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3341533112
Short name T356
Test name
Test status
Simulation time 26947189 ps
CPU time 0.52 seconds
Started Jul 02 09:28:32 AM PDT 24
Finished Jul 02 09:28:34 AM PDT 24
Peak memory 183028 kb
Host smart-47f6eb48-4173-4908-b38a-d6ab6781e1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341533112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3341533112
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1227032459
Short name T357
Test name
Test status
Simulation time 152743385817 ps
CPU time 234.26 seconds
Started Jul 02 09:28:27 AM PDT 24
Finished Jul 02 09:32:23 AM PDT 24
Peak memory 183184 kb
Host smart-8cd148c1-2195-43dd-8d3b-3e4c0c17e32e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227032459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1227032459
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1543290577
Short name T158
Test name
Test status
Simulation time 1581486028423 ps
CPU time 856.61 seconds
Started Jul 02 09:28:32 AM PDT 24
Finished Jul 02 09:42:50 AM PDT 24
Peak memory 183100 kb
Host smart-ea163b58-a0fa-475c-b0a8-fcf93987d273
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543290577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1543290577
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1362725211
Short name T144
Test name
Test status
Simulation time 267328841056 ps
CPU time 1058.42 seconds
Started Jul 02 09:28:28 AM PDT 24
Finished Jul 02 09:46:08 AM PDT 24
Peak memory 191376 kb
Host smart-1bb10f45-1b2f-4723-ad65-9641dd9390ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362725211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1362725211
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1006777990
Short name T57
Test name
Test status
Simulation time 131153015534 ps
CPU time 128.08 seconds
Started Jul 02 09:28:25 AM PDT 24
Finished Jul 02 09:30:34 AM PDT 24
Peak memory 191312 kb
Host smart-c74219a9-fdc4-41fb-b9a8-b044d8bfcda3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006777990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1006777990
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2625144031
Short name T313
Test name
Test status
Simulation time 30906979605 ps
CPU time 15.33 seconds
Started Jul 02 09:28:32 AM PDT 24
Finished Jul 02 09:28:49 AM PDT 24
Peak memory 183104 kb
Host smart-31549c8a-94ae-48a2-b66c-9c628b7674a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625144031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2625144031
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.4119586884
Short name T394
Test name
Test status
Simulation time 102540128873 ps
CPU time 148.04 seconds
Started Jul 02 09:28:27 AM PDT 24
Finished Jul 02 09:30:57 AM PDT 24
Peak memory 183096 kb
Host smart-ea666308-4d45-415a-9897-23da3576145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119586884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.4119586884
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2637528497
Short name T279
Test name
Test status
Simulation time 177575172324 ps
CPU time 562.17 seconds
Started Jul 02 09:28:26 AM PDT 24
Finished Jul 02 09:37:49 AM PDT 24
Peak memory 191372 kb
Host smart-652cf605-68f0-429e-aca7-d9ba499fbc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637528497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2637528497
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.551171866
Short name T365
Test name
Test status
Simulation time 3170721593 ps
CPU time 29.15 seconds
Started Jul 02 09:28:30 AM PDT 24
Finished Jul 02 09:29:00 AM PDT 24
Peak memory 191372 kb
Host smart-249f63cf-e952-4cd6-81c4-181708723057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551171866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.551171866
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.962838805
Short name T419
Test name
Test status
Simulation time 216832608324 ps
CPU time 113.66 seconds
Started Jul 02 09:28:34 AM PDT 24
Finished Jul 02 09:30:28 AM PDT 24
Peak memory 183168 kb
Host smart-9045e6d9-6a99-4d3b-afd6-0af394ea99a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962838805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.962838805
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.956279732
Short name T373
Test name
Test status
Simulation time 278138018903 ps
CPU time 146.05 seconds
Started Jul 02 09:28:33 AM PDT 24
Finished Jul 02 09:31:00 AM PDT 24
Peak memory 183156 kb
Host smart-538b15f7-ce25-447e-970b-658770122439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956279732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.956279732
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.964849804
Short name T263
Test name
Test status
Simulation time 29230837615 ps
CPU time 39.27 seconds
Started Jul 02 09:28:34 AM PDT 24
Finished Jul 02 09:29:14 AM PDT 24
Peak memory 183112 kb
Host smart-377806a5-79f6-47b7-9fb3-c1d58933d47b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964849804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.964849804
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3789454374
Short name T435
Test name
Test status
Simulation time 172811546 ps
CPU time 1.14 seconds
Started Jul 02 09:28:33 AM PDT 24
Finished Jul 02 09:28:35 AM PDT 24
Peak memory 193644 kb
Host smart-caf03ce0-8e7f-4aa6-a856-996a7e113d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789454374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3789454374
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2179235403
Short name T318
Test name
Test status
Simulation time 44299741186 ps
CPU time 18.85 seconds
Started Jul 02 09:28:32 AM PDT 24
Finished Jul 02 09:28:52 AM PDT 24
Peak memory 183164 kb
Host smart-8f7b1768-f9be-4624-ba0f-69dabc4b12ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179235403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2179235403
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.142538078
Short name T371
Test name
Test status
Simulation time 65617699931 ps
CPU time 52.49 seconds
Started Jul 02 09:28:31 AM PDT 24
Finished Jul 02 09:29:25 AM PDT 24
Peak memory 183144 kb
Host smart-8997f2c9-1861-4019-90a6-63efd7802a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142538078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.142538078
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3576212362
Short name T283
Test name
Test status
Simulation time 16179837084 ps
CPU time 24.84 seconds
Started Jul 02 09:28:32 AM PDT 24
Finished Jul 02 09:28:58 AM PDT 24
Peak memory 183052 kb
Host smart-d36df9fb-5338-4da8-ba95-4a17905c481c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576212362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3576212362
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2006676177
Short name T354
Test name
Test status
Simulation time 1459052463 ps
CPU time 1.91 seconds
Started Jul 02 09:28:32 AM PDT 24
Finished Jul 02 09:28:35 AM PDT 24
Peak memory 183120 kb
Host smart-e5b39639-ec71-4a9a-b2b0-207df933d3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006676177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2006676177
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1097230834
Short name T254
Test name
Test status
Simulation time 182993358510 ps
CPU time 172.54 seconds
Started Jul 02 09:28:31 AM PDT 24
Finished Jul 02 09:31:25 AM PDT 24
Peak memory 183148 kb
Host smart-1efef499-a3a6-4cb7-a561-f5b370add590
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097230834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1097230834
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.4231846747
Short name T428
Test name
Test status
Simulation time 183421290129 ps
CPU time 249.19 seconds
Started Jul 02 09:28:31 AM PDT 24
Finished Jul 02 09:32:42 AM PDT 24
Peak memory 183180 kb
Host smart-9f97074c-88bd-444d-b534-6816a5a3addd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231846747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.4231846747
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1493957199
Short name T256
Test name
Test status
Simulation time 29472163572 ps
CPU time 1031.34 seconds
Started Jul 02 09:28:33 AM PDT 24
Finished Jul 02 09:45:45 AM PDT 24
Peak memory 183156 kb
Host smart-ac792633-bf5f-4fc8-a1b4-c29c103e5975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493957199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1493957199
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.467957800
Short name T222
Test name
Test status
Simulation time 308636442283 ps
CPU time 133.12 seconds
Started Jul 02 09:28:31 AM PDT 24
Finished Jul 02 09:30:44 AM PDT 24
Peak memory 191388 kb
Host smart-f4c1bee9-bd94-4243-b759-3f2acd3bf331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467957800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.467957800
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4233242957
Short name T105
Test name
Test status
Simulation time 148042368743 ps
CPU time 235.98 seconds
Started Jul 02 09:28:36 AM PDT 24
Finished Jul 02 09:32:33 AM PDT 24
Peak memory 183124 kb
Host smart-837941cd-f0bc-4db1-a9fa-c588baa1d426
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233242957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4233242957
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.4014593528
Short name T383
Test name
Test status
Simulation time 962626083322 ps
CPU time 375.76 seconds
Started Jul 02 09:28:35 AM PDT 24
Finished Jul 02 09:34:52 AM PDT 24
Peak memory 183148 kb
Host smart-e7546339-7ca0-4b77-9446-8fbaa20fa6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014593528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4014593528
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3726462610
Short name T165
Test name
Test status
Simulation time 101398412616 ps
CPU time 458.46 seconds
Started Jul 02 09:28:42 AM PDT 24
Finished Jul 02 09:36:21 AM PDT 24
Peak memory 191348 kb
Host smart-238ab836-c8a7-4c1f-bc62-164e1af728c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726462610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3726462610
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3244340962
Short name T247
Test name
Test status
Simulation time 138631748294 ps
CPU time 92.87 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:30:17 AM PDT 24
Peak memory 183192 kb
Host smart-9757c805-fafa-471b-a760-6d31feb3f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244340962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3244340962
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.573577179
Short name T12
Test name
Test status
Simulation time 80400716684 ps
CPU time 338.36 seconds
Started Jul 02 09:28:36 AM PDT 24
Finished Jul 02 09:34:15 AM PDT 24
Peak memory 206088 kb
Host smart-97645580-9d76-4db4-b032-7a151651d34d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573577179 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.573577179
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3725477206
Short name T5
Test name
Test status
Simulation time 38771498679 ps
CPU time 57.38 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:29:41 AM PDT 24
Peak memory 183132 kb
Host smart-d2582233-fbea-476d-bc6a-5670964741e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725477206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3725477206
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.745294282
Short name T324
Test name
Test status
Simulation time 62085939166 ps
CPU time 84.61 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:30:09 AM PDT 24
Peak memory 191348 kb
Host smart-6dc9c44c-94ae-4831-9fcc-dd8e1d4cb694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745294282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.745294282
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3505504920
Short name T447
Test name
Test status
Simulation time 475560306502 ps
CPU time 152.32 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:31:16 AM PDT 24
Peak memory 183316 kb
Host smart-29bf4608-73a3-4bf5-aeab-0b4f6eec6276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505504920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3505504920
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.772130416
Short name T118
Test name
Test status
Simulation time 2601461126744 ps
CPU time 1059.83 seconds
Started Jul 02 09:28:41 AM PDT 24
Finished Jul 02 09:46:22 AM PDT 24
Peak memory 191352 kb
Host smart-13d51260-7ca1-43c4-a5d8-ae2d787f9d9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772130416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
772130416
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1451972282
Short name T139
Test name
Test status
Simulation time 299802577429 ps
CPU time 434.35 seconds
Started Jul 02 09:28:03 AM PDT 24
Finished Jul 02 09:35:19 AM PDT 24
Peak memory 183168 kb
Host smart-ead4d4f6-2098-434d-be48-028f174f3db1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451972282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1451972282
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.401898309
Short name T405
Test name
Test status
Simulation time 111488497573 ps
CPU time 28.57 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:28:32 AM PDT 24
Peak memory 183144 kb
Host smart-d3e8cca6-f17a-4a62-80f7-c42522bf7077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401898309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.401898309
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3774898078
Short name T14
Test name
Test status
Simulation time 86388682 ps
CPU time 0.95 seconds
Started Jul 02 09:28:03 AM PDT 24
Finished Jul 02 09:28:05 AM PDT 24
Peak memory 214516 kb
Host smart-6ce9eefa-2918-4391-b6ff-5263fafaed76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774898078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3774898078
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3526921007
Short name T449
Test name
Test status
Simulation time 26894976515 ps
CPU time 44.5 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:29:28 AM PDT 24
Peak memory 183128 kb
Host smart-88b1de17-8c3d-4b6f-9e47-6ef2fe49f1ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526921007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3526921007
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1273966177
Short name T41
Test name
Test status
Simulation time 122882566343 ps
CPU time 97.94 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:30:22 AM PDT 24
Peak memory 183144 kb
Host smart-1323cb65-568d-42fd-a35a-b945f3d59c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273966177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1273966177
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2168923371
Short name T103
Test name
Test status
Simulation time 384801372785 ps
CPU time 593.92 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:38:38 AM PDT 24
Peak memory 191352 kb
Host smart-9a538b01-0927-4577-9e95-459fd945b0ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168923371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2168923371
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1295103036
Short name T205
Test name
Test status
Simulation time 21029989147 ps
CPU time 17.91 seconds
Started Jul 02 09:28:45 AM PDT 24
Finished Jul 02 09:29:03 AM PDT 24
Peak memory 191364 kb
Host smart-4a8d590b-ce52-449e-a382-2c3268616b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295103036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1295103036
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2646007313
Short name T393
Test name
Test status
Simulation time 711835020844 ps
CPU time 241.42 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:32:45 AM PDT 24
Peak memory 183164 kb
Host smart-11577de5-2324-454a-8fa5-fc9d9c681e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646007313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2646007313
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2704697677
Short name T257
Test name
Test status
Simulation time 537983396926 ps
CPU time 257.25 seconds
Started Jul 02 09:28:44 AM PDT 24
Finished Jul 02 09:33:02 AM PDT 24
Peak memory 183136 kb
Host smart-8a73c41f-bbbd-4dc0-867e-5c358ce9cdb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704697677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2704697677
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3694802819
Short name T360
Test name
Test status
Simulation time 102454236758 ps
CPU time 79.82 seconds
Started Jul 02 09:28:44 AM PDT 24
Finished Jul 02 09:30:05 AM PDT 24
Peak memory 183176 kb
Host smart-e4e027a8-38d0-46c1-8de9-f95cd04111a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694802819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3694802819
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1814930698
Short name T446
Test name
Test status
Simulation time 33895572760 ps
CPU time 55.42 seconds
Started Jul 02 09:28:43 AM PDT 24
Finished Jul 02 09:29:39 AM PDT 24
Peak memory 183172 kb
Host smart-feb405cf-1477-4306-8331-8541ca53e0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814930698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1814930698
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3618609779
Short name T137
Test name
Test status
Simulation time 12283215807 ps
CPU time 23.38 seconds
Started Jul 02 09:28:42 AM PDT 24
Finished Jul 02 09:29:07 AM PDT 24
Peak memory 194856 kb
Host smart-6521c3b7-72f6-4732-a3bf-18878dc6dc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618609779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3618609779
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3659891468
Short name T109
Test name
Test status
Simulation time 518096315731 ps
CPU time 2556.92 seconds
Started Jul 02 09:28:51 AM PDT 24
Finished Jul 02 10:11:29 AM PDT 24
Peak memory 191296 kb
Host smart-0861598a-3f9e-4041-8d66-267958695274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659891468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3659891468
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2707165701
Short name T196
Test name
Test status
Simulation time 1659924330921 ps
CPU time 873.64 seconds
Started Jul 02 09:28:47 AM PDT 24
Finished Jul 02 09:43:22 AM PDT 24
Peak memory 183132 kb
Host smart-33d92d1f-543d-4960-8943-a2fdbdb995b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707165701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2707165701
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.4293859875
Short name T412
Test name
Test status
Simulation time 134090465222 ps
CPU time 64.18 seconds
Started Jul 02 09:28:48 AM PDT 24
Finished Jul 02 09:29:52 AM PDT 24
Peak memory 183156 kb
Host smart-38b84db8-8aec-4797-b58e-b454c7030ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293859875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.4293859875
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.202193233
Short name T104
Test name
Test status
Simulation time 3685632696857 ps
CPU time 757.29 seconds
Started Jul 02 09:28:50 AM PDT 24
Finished Jul 02 09:41:27 AM PDT 24
Peak memory 191308 kb
Host smart-f05edaaf-ab26-4398-af97-fa69396264bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202193233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.202193233
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.304696365
Short name T321
Test name
Test status
Simulation time 49975010679 ps
CPU time 40.64 seconds
Started Jul 02 09:28:50 AM PDT 24
Finished Jul 02 09:29:31 AM PDT 24
Peak memory 183120 kb
Host smart-75502ae5-bb43-4e58-a00e-d617463d48a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304696365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.304696365
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.420902432
Short name T372
Test name
Test status
Simulation time 428473955918 ps
CPU time 153.85 seconds
Started Jul 02 09:28:55 AM PDT 24
Finished Jul 02 09:31:30 AM PDT 24
Peak memory 194740 kb
Host smart-92d6a54d-63d9-45d4-97d9-22ca630a0d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420902432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
420902432
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1183077939
Short name T391
Test name
Test status
Simulation time 48348102165 ps
CPU time 24.74 seconds
Started Jul 02 09:28:50 AM PDT 24
Finished Jul 02 09:29:15 AM PDT 24
Peak memory 183104 kb
Host smart-f51f919f-6691-4ca1-a494-d361564b26ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183077939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1183077939
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.995546689
Short name T364
Test name
Test status
Simulation time 56212276844 ps
CPU time 74.08 seconds
Started Jul 02 09:28:51 AM PDT 24
Finished Jul 02 09:30:05 AM PDT 24
Peak memory 183132 kb
Host smart-e3747bc8-be19-44ac-8231-b7a5b0093067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995546689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.995546689
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2816092200
Short name T442
Test name
Test status
Simulation time 367587175143 ps
CPU time 166.83 seconds
Started Jul 02 09:28:51 AM PDT 24
Finished Jul 02 09:31:38 AM PDT 24
Peak memory 191336 kb
Host smart-d569d9b8-eca0-42a9-9781-1a62f9475afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816092200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2816092200
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2380057009
Short name T423
Test name
Test status
Simulation time 4394456344 ps
CPU time 7.03 seconds
Started Jul 02 09:28:56 AM PDT 24
Finished Jul 02 09:29:04 AM PDT 24
Peak memory 183164 kb
Host smart-4e168016-6e25-4499-8f6d-0ed4854dea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380057009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2380057009
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3344436417
Short name T172
Test name
Test status
Simulation time 260746764628 ps
CPU time 704.36 seconds
Started Jul 02 09:28:51 AM PDT 24
Finished Jul 02 09:40:36 AM PDT 24
Peak memory 191320 kb
Host smart-d3966ca2-b326-489d-9e0b-bdf2379eb1a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344436417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3344436417
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2185451738
Short name T259
Test name
Test status
Simulation time 63523231252 ps
CPU time 31.44 seconds
Started Jul 02 09:28:55 AM PDT 24
Finished Jul 02 09:29:27 AM PDT 24
Peak memory 183148 kb
Host smart-50f0bcff-9e09-41dc-9b76-8f49d7a8e1c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185451738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2185451738
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1701177799
Short name T420
Test name
Test status
Simulation time 98745226155 ps
CPU time 140.38 seconds
Started Jul 02 09:28:55 AM PDT 24
Finished Jul 02 09:31:16 AM PDT 24
Peak memory 183168 kb
Host smart-f21746be-e1ba-48d6-95f2-10c0ed17aefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701177799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1701177799
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1086420916
Short name T289
Test name
Test status
Simulation time 49906813266 ps
CPU time 80.71 seconds
Started Jul 02 09:28:57 AM PDT 24
Finished Jul 02 09:30:18 AM PDT 24
Peak memory 183124 kb
Host smart-ad8890d7-23ea-4198-81f9-55b36a55d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086420916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1086420916
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.4113702168
Short name T154
Test name
Test status
Simulation time 285679913313 ps
CPU time 580.82 seconds
Started Jul 02 09:28:54 AM PDT 24
Finished Jul 02 09:38:35 AM PDT 24
Peak memory 191320 kb
Host smart-50097184-f044-41ce-8380-f6f74ccf63e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113702168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.4113702168
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1804339499
Short name T36
Test name
Test status
Simulation time 60786458678 ps
CPU time 440.65 seconds
Started Jul 02 09:28:56 AM PDT 24
Finished Jul 02 09:36:17 AM PDT 24
Peak memory 208372 kb
Host smart-02969a1b-5c20-4b1c-b40f-08cf10374e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804339499 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1804339499
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.192517250
Short name T270
Test name
Test status
Simulation time 37859154019 ps
CPU time 57.11 seconds
Started Jul 02 09:28:54 AM PDT 24
Finished Jul 02 09:29:52 AM PDT 24
Peak memory 183172 kb
Host smart-70689b7d-a6a6-4fa1-873a-1007372303d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192517250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.192517250
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.588700928
Short name T20
Test name
Test status
Simulation time 113255417423 ps
CPU time 151.51 seconds
Started Jul 02 09:28:55 AM PDT 24
Finished Jul 02 09:31:27 AM PDT 24
Peak memory 183316 kb
Host smart-5045ce40-2123-4cdd-88ed-78d5d99584ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588700928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.588700928
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1878254548
Short name T244
Test name
Test status
Simulation time 105174233645 ps
CPU time 884.22 seconds
Started Jul 02 09:28:57 AM PDT 24
Finished Jul 02 09:43:42 AM PDT 24
Peak memory 191332 kb
Host smart-58ec1195-9544-4ec0-8a9f-ee920511628b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878254548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1878254548
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1476673617
Short name T358
Test name
Test status
Simulation time 21819233 ps
CPU time 0.52 seconds
Started Jul 02 09:29:00 AM PDT 24
Finished Jul 02 09:29:01 AM PDT 24
Peak memory 182980 kb
Host smart-d2da3a94-b17f-4e45-ad56-185e1f43fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476673617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1476673617
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3565005341
Short name T123
Test name
Test status
Simulation time 276532545814 ps
CPU time 238 seconds
Started Jul 02 09:28:59 AM PDT 24
Finished Jul 02 09:32:57 AM PDT 24
Peak memory 183176 kb
Host smart-4ae0de0d-25d1-4c99-8423-5866da95bc23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565005341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3565005341
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1300073467
Short name T387
Test name
Test status
Simulation time 349061377182 ps
CPU time 139.96 seconds
Started Jul 02 09:29:02 AM PDT 24
Finished Jul 02 09:31:22 AM PDT 24
Peak memory 183120 kb
Host smart-6202339f-73e7-4cbb-abdf-81e33ce40a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300073467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1300073467
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4131176067
Short name T438
Test name
Test status
Simulation time 26967474594 ps
CPU time 39.93 seconds
Started Jul 02 09:28:59 AM PDT 24
Finished Jul 02 09:29:39 AM PDT 24
Peak memory 183152 kb
Host smart-69ee279d-d97e-4ccc-bd8b-4bef86e1c72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131176067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4131176067
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.703394622
Short name T237
Test name
Test status
Simulation time 57541809475 ps
CPU time 24.62 seconds
Started Jul 02 09:29:04 AM PDT 24
Finished Jul 02 09:29:29 AM PDT 24
Peak memory 183140 kb
Host smart-4233311c-ea69-430a-a5c6-b96a26b80d40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703394622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.703394622
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1225439759
Short name T369
Test name
Test status
Simulation time 328251362313 ps
CPU time 51.95 seconds
Started Jul 02 09:29:03 AM PDT 24
Finished Jul 02 09:29:55 AM PDT 24
Peak memory 183168 kb
Host smart-6d383a16-1f70-4e76-a162-8ac0834f0f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225439759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1225439759
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.257373570
Short name T348
Test name
Test status
Simulation time 323946368387 ps
CPU time 466.31 seconds
Started Jul 02 09:29:02 AM PDT 24
Finished Jul 02 09:36:48 AM PDT 24
Peak memory 191348 kb
Host smart-88c7b395-61e1-4b80-b984-64191b0ef9d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257373570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.257373570
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.875101338
Short name T437
Test name
Test status
Simulation time 100990627 ps
CPU time 0.61 seconds
Started Jul 02 09:29:04 AM PDT 24
Finished Jul 02 09:29:04 AM PDT 24
Peak memory 183032 kb
Host smart-d4c4cbdd-c893-4c31-bab7-1c4ea220d323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875101338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.875101338
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.4138620435
Short name T385
Test name
Test status
Simulation time 835293779223 ps
CPU time 300.72 seconds
Started Jul 02 09:29:02 AM PDT 24
Finished Jul 02 09:34:03 AM PDT 24
Peak memory 191332 kb
Host smart-2358eb17-51c7-4f70-9762-5440a342c165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138620435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.4138620435
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2699559814
Short name T182
Test name
Test status
Simulation time 8925686154 ps
CPU time 16.03 seconds
Started Jul 02 09:29:07 AM PDT 24
Finished Jul 02 09:29:24 AM PDT 24
Peak memory 183148 kb
Host smart-691ee1f5-1a4b-4eef-85f0-c4338b72ef3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699559814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2699559814
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4026729040
Short name T377
Test name
Test status
Simulation time 76887131690 ps
CPU time 65.28 seconds
Started Jul 02 09:29:10 AM PDT 24
Finished Jul 02 09:30:15 AM PDT 24
Peak memory 183188 kb
Host smart-ba485cbf-e5e3-4ae8-b61c-e60e12d3132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026729040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4026729040
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3285383753
Short name T45
Test name
Test status
Simulation time 130758625454 ps
CPU time 181.36 seconds
Started Jul 02 09:29:04 AM PDT 24
Finished Jul 02 09:32:06 AM PDT 24
Peak memory 191364 kb
Host smart-5e020a5a-9cc5-4a99-9948-d438a897249f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285383753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3285383753
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3837844633
Short name T198
Test name
Test status
Simulation time 35322141190 ps
CPU time 192.45 seconds
Started Jul 02 09:29:10 AM PDT 24
Finished Jul 02 09:32:23 AM PDT 24
Peak memory 191384 kb
Host smart-d3f989d5-1137-4cc8-96e5-4574861e250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837844633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3837844633
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.2225354069
Short name T35
Test name
Test status
Simulation time 90639609618 ps
CPU time 320.85 seconds
Started Jul 02 09:29:07 AM PDT 24
Finished Jul 02 09:34:28 AM PDT 24
Peak memory 206080 kb
Host smart-f266090c-8360-46ba-a47a-a59767e09a80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225354069 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.2225354069
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.575584733
Short name T290
Test name
Test status
Simulation time 23939481453 ps
CPU time 24 seconds
Started Jul 02 09:29:08 AM PDT 24
Finished Jul 02 09:29:32 AM PDT 24
Peak memory 183160 kb
Host smart-d13c27d9-739b-4843-ac6f-f5dfbbff5aed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575584733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.575584733
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1674381844
Short name T370
Test name
Test status
Simulation time 444655132708 ps
CPU time 169.1 seconds
Started Jul 02 09:29:07 AM PDT 24
Finished Jul 02 09:31:57 AM PDT 24
Peak memory 183188 kb
Host smart-26a00e48-ae78-4563-a884-a154ef3151d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674381844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1674381844
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1970677056
Short name T398
Test name
Test status
Simulation time 146995789023 ps
CPU time 113.52 seconds
Started Jul 02 09:29:06 AM PDT 24
Finished Jul 02 09:31:00 AM PDT 24
Peak memory 191368 kb
Host smart-597df735-f22a-4759-8428-c115813b7c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970677056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1970677056
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3880603168
Short name T448
Test name
Test status
Simulation time 23721850766 ps
CPU time 11.5 seconds
Started Jul 02 09:29:09 AM PDT 24
Finished Jul 02 09:29:21 AM PDT 24
Peak memory 183188 kb
Host smart-2930dffb-6c05-4e80-9bac-a95fe7b7fd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880603168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3880603168
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1185037409
Short name T204
Test name
Test status
Simulation time 2172046690110 ps
CPU time 1159.87 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:47:24 AM PDT 24
Peak memory 183128 kb
Host smart-dc2a73e7-bf73-4c9d-8f7d-973c2acde3b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185037409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1185037409
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4205093606
Short name T382
Test name
Test status
Simulation time 74926517361 ps
CPU time 107.39 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:29:49 AM PDT 24
Peak memory 183180 kb
Host smart-e909f3f9-5414-4c93-aa55-f41e49e59a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205093606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4205093606
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2807845688
Short name T341
Test name
Test status
Simulation time 23996484224 ps
CPU time 51.63 seconds
Started Jul 02 09:28:04 AM PDT 24
Finished Jul 02 09:28:57 AM PDT 24
Peak memory 183144 kb
Host smart-ad60b805-21c2-4c66-ac4c-4ff3b747e1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807845688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2807845688
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.3106345357
Short name T347
Test name
Test status
Simulation time 490539637592 ps
CPU time 279.14 seconds
Started Jul 02 09:29:12 AM PDT 24
Finished Jul 02 09:33:51 AM PDT 24
Peak memory 191328 kb
Host smart-6ba7554f-a8c5-4d75-b424-e669071828bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106345357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3106345357
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1492806593
Short name T117
Test name
Test status
Simulation time 151133911150 ps
CPU time 259.66 seconds
Started Jul 02 09:29:09 AM PDT 24
Finished Jul 02 09:33:29 AM PDT 24
Peak memory 194920 kb
Host smart-0c115c5e-cd84-432c-be2a-45170b81efe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492806593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1492806593
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3278227260
Short name T280
Test name
Test status
Simulation time 163776338337 ps
CPU time 155.19 seconds
Started Jul 02 09:29:16 AM PDT 24
Finished Jul 02 09:31:51 AM PDT 24
Peak memory 191372 kb
Host smart-ef3f4725-4774-49a5-97d9-7739609f1406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278227260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3278227260
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1878093616
Short name T216
Test name
Test status
Simulation time 262146806456 ps
CPU time 852.41 seconds
Started Jul 02 09:29:17 AM PDT 24
Finished Jul 02 09:43:30 AM PDT 24
Peak memory 191308 kb
Host smart-ebbe2551-0c24-41e9-960f-0eabbeba785e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878093616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1878093616
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1454951626
Short name T342
Test name
Test status
Simulation time 60189696417 ps
CPU time 97.02 seconds
Started Jul 02 09:29:13 AM PDT 24
Finished Jul 02 09:30:51 AM PDT 24
Peak memory 191332 kb
Host smart-d797118f-1c46-4fcd-858b-cbd75805b5cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454951626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1454951626
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1463250659
Short name T201
Test name
Test status
Simulation time 581277734499 ps
CPU time 172.16 seconds
Started Jul 02 09:29:19 AM PDT 24
Finished Jul 02 09:32:11 AM PDT 24
Peak memory 191344 kb
Host smart-fa0215b5-b07f-40e5-80d2-d11172150d4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463250659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1463250659
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1891732399
Short name T176
Test name
Test status
Simulation time 56342830609 ps
CPU time 102.2 seconds
Started Jul 02 09:29:18 AM PDT 24
Finished Jul 02 09:31:00 AM PDT 24
Peak memory 191372 kb
Host smart-7d17c578-2bd3-46fa-90ee-d2b55903b78c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891732399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1891732399
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1992484223
Short name T315
Test name
Test status
Simulation time 462997570369 ps
CPU time 688.07 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:39:31 AM PDT 24
Peak memory 183148 kb
Host smart-8056f594-345a-4382-9b8a-f66d4e737e29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992484223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1992484223
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3632655278
Short name T422
Test name
Test status
Simulation time 163143728204 ps
CPU time 211.96 seconds
Started Jul 02 09:28:05 AM PDT 24
Finished Jul 02 09:31:37 AM PDT 24
Peak memory 183144 kb
Host smart-5a9dd28c-7ddc-4539-9dba-0aab10d0eb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632655278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3632655278
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3627476101
Short name T260
Test name
Test status
Simulation time 45459654777 ps
CPU time 80.77 seconds
Started Jul 02 09:28:06 AM PDT 24
Finished Jul 02 09:29:27 AM PDT 24
Peak memory 183108 kb
Host smart-86645394-c6df-428b-a0fa-834ef2f37745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627476101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3627476101
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4124140909
Short name T351
Test name
Test status
Simulation time 116301877477 ps
CPU time 183.69 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:31:05 AM PDT 24
Peak memory 191328 kb
Host smart-76b172fd-95e3-4be1-924a-c9db1c760869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124140909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4124140909
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2008263405
Short name T451
Test name
Test status
Simulation time 483384163014 ps
CPU time 589.51 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:37:51 AM PDT 24
Peak memory 191348 kb
Host smart-772a2df4-387d-4f6c-96e6-da77d6747d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008263405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2008263405
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3586364255
Short name T186
Test name
Test status
Simulation time 38131429083 ps
CPU time 93.46 seconds
Started Jul 02 09:29:21 AM PDT 24
Finished Jul 02 09:30:54 AM PDT 24
Peak memory 191344 kb
Host smart-aba9e16b-af1c-483f-a390-64821ac20366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586364255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3586364255
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3739686947
Short name T2
Test name
Test status
Simulation time 229849482604 ps
CPU time 93.48 seconds
Started Jul 02 09:29:23 AM PDT 24
Finished Jul 02 09:30:56 AM PDT 24
Peak memory 191352 kb
Host smart-4b321987-30b4-4e30-ab89-e1281b5ad7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739686947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3739686947
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.693964513
Short name T234
Test name
Test status
Simulation time 165536142868 ps
CPU time 446.18 seconds
Started Jul 02 09:29:22 AM PDT 24
Finished Jul 02 09:36:49 AM PDT 24
Peak memory 191356 kb
Host smart-8e7b8d0c-9ae3-4f3f-9d04-6e07093ced3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693964513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.693964513
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3534777577
Short name T217
Test name
Test status
Simulation time 144839732007 ps
CPU time 946.39 seconds
Started Jul 02 09:29:22 AM PDT 24
Finished Jul 02 09:45:09 AM PDT 24
Peak memory 191368 kb
Host smart-a01d32ef-4436-4f3a-bf94-cc24082677d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534777577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3534777577
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3222269005
Short name T208
Test name
Test status
Simulation time 238171046021 ps
CPU time 499.08 seconds
Started Jul 02 09:29:21 AM PDT 24
Finished Jul 02 09:37:41 AM PDT 24
Peak memory 193804 kb
Host smart-0ac59c08-607e-417e-bf49-91bf369d30fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222269005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3222269005
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2527692032
Short name T106
Test name
Test status
Simulation time 54904777928 ps
CPU time 71.52 seconds
Started Jul 02 09:29:26 AM PDT 24
Finished Jul 02 09:30:38 AM PDT 24
Peak memory 194912 kb
Host smart-bbc0d240-d1d4-4b28-8b9f-1a0464f17ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527692032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2527692032
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1493697451
Short name T180
Test name
Test status
Simulation time 85839708725 ps
CPU time 1276.56 seconds
Started Jul 02 09:29:24 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 191324 kb
Host smart-8e54aad8-075c-4103-9fe5-fffd812b486c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493697451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1493697451
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1365704457
Short name T439
Test name
Test status
Simulation time 213461112497 ps
CPU time 667.39 seconds
Started Jul 02 09:29:28 AM PDT 24
Finished Jul 02 09:40:36 AM PDT 24
Peak memory 191308 kb
Host smart-c80aee40-e054-4f6c-ab20-ff144b0459c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365704457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1365704457
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.724847350
Short name T129
Test name
Test status
Simulation time 64305773046 ps
CPU time 403.23 seconds
Started Jul 02 09:29:25 AM PDT 24
Finished Jul 02 09:36:09 AM PDT 24
Peak memory 191284 kb
Host smart-fe9c582d-37c9-4441-aee2-243fc884aa38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724847350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.724847350
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2302313338
Short name T183
Test name
Test status
Simulation time 175892153702 ps
CPU time 624.94 seconds
Started Jul 02 09:29:26 AM PDT 24
Finished Jul 02 09:39:51 AM PDT 24
Peak memory 191364 kb
Host smart-4f8da069-5d46-4c33-8eee-9e9540c8ef0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302313338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2302313338
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3592801232
Short name T258
Test name
Test status
Simulation time 86808376514 ps
CPU time 136.47 seconds
Started Jul 02 09:28:01 AM PDT 24
Finished Jul 02 09:30:18 AM PDT 24
Peak memory 183160 kb
Host smart-2ed63529-1fce-46ae-ae83-174686658a3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592801232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3592801232
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1223644074
Short name T427
Test name
Test status
Simulation time 339508345396 ps
CPU time 146.49 seconds
Started Jul 02 09:28:03 AM PDT 24
Finished Jul 02 09:30:31 AM PDT 24
Peak memory 183188 kb
Host smart-c71ffd3e-7526-484d-bf0c-7ecaacbc800d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223644074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1223644074
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1475664592
Short name T23
Test name
Test status
Simulation time 162165152 ps
CPU time 0.83 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:28:04 AM PDT 24
Peak memory 183008 kb
Host smart-eabb4103-dc36-43b8-a81d-3f4eaf83d1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475664592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1475664592
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.247306537
Short name T230
Test name
Test status
Simulation time 1342153656551 ps
CPU time 582.54 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:37:46 AM PDT 24
Peak memory 191368 kb
Host smart-bfe0259b-a942-4d10-8acd-8edbfdb018f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247306537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.247306537
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.307798389
Short name T113
Test name
Test status
Simulation time 136433523782 ps
CPU time 1005.61 seconds
Started Jul 02 09:29:26 AM PDT 24
Finished Jul 02 09:46:12 AM PDT 24
Peak memory 191312 kb
Host smart-4c715c06-9fc1-4435-a116-c0370da4f09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307798389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.307798389
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.545233451
Short name T334
Test name
Test status
Simulation time 113089533693 ps
CPU time 109.59 seconds
Started Jul 02 09:29:25 AM PDT 24
Finished Jul 02 09:31:15 AM PDT 24
Peak memory 191320 kb
Host smart-a0a2700b-dfb0-4067-91c9-2d2f6728b2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545233451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.545233451
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3249152766
Short name T327
Test name
Test status
Simulation time 41342125242 ps
CPU time 88.64 seconds
Started Jul 02 09:29:25 AM PDT 24
Finished Jul 02 09:30:53 AM PDT 24
Peak memory 183192 kb
Host smart-10672b4e-fd10-4dbd-b245-83682a7be5e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249152766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3249152766
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2560333750
Short name T179
Test name
Test status
Simulation time 2697201392154 ps
CPU time 1177.94 seconds
Started Jul 02 09:29:27 AM PDT 24
Finished Jul 02 09:49:05 AM PDT 24
Peak memory 191308 kb
Host smart-9141111c-1f7d-4308-9a4c-4e00a15764c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560333750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2560333750
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.321269141
Short name T340
Test name
Test status
Simulation time 369900790507 ps
CPU time 533.27 seconds
Started Jul 02 09:29:27 AM PDT 24
Finished Jul 02 09:38:21 AM PDT 24
Peak memory 191384 kb
Host smart-cda5cabf-4b99-4d2e-8cf8-c984d86846e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321269141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.321269141
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.563481699
Short name T295
Test name
Test status
Simulation time 34511428621 ps
CPU time 48.56 seconds
Started Jul 02 09:29:32 AM PDT 24
Finished Jul 02 09:30:21 AM PDT 24
Peak memory 183168 kb
Host smart-2d76ffa8-d030-499e-bbb2-e0fcb97a3d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563481699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.563481699
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3422225212
Short name T145
Test name
Test status
Simulation time 338450993059 ps
CPU time 255.62 seconds
Started Jul 02 09:29:28 AM PDT 24
Finished Jul 02 09:33:44 AM PDT 24
Peak memory 191372 kb
Host smart-d0c0784a-e026-47c9-b089-86f6aa77fe79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422225212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3422225212
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2951868242
Short name T345
Test name
Test status
Simulation time 577529227808 ps
CPU time 284.72 seconds
Started Jul 02 09:28:00 AM PDT 24
Finished Jul 02 09:32:45 AM PDT 24
Peak memory 183104 kb
Host smart-fda728db-946a-44ac-bc25-76846b410591
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951868242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2951868242
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.4134003669
Short name T22
Test name
Test status
Simulation time 113272049532 ps
CPU time 43.9 seconds
Started Jul 02 09:28:02 AM PDT 24
Finished Jul 02 09:28:48 AM PDT 24
Peak memory 183168 kb
Host smart-00f59029-98c8-48f4-b243-1f981a1ab280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134003669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.4134003669
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2599462136
Short name T384
Test name
Test status
Simulation time 540420652 ps
CPU time 0.94 seconds
Started Jul 02 09:28:05 AM PDT 24
Finished Jul 02 09:28:07 AM PDT 24
Peak memory 192936 kb
Host smart-9a506845-4cae-47b8-b0b9-1cbc8c67ac5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599462136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2599462136
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3059438734
Short name T59
Test name
Test status
Simulation time 230660280155 ps
CPU time 332.56 seconds
Started Jul 02 09:28:06 AM PDT 24
Finished Jul 02 09:33:39 AM PDT 24
Peak memory 194588 kb
Host smart-c08a7d49-9acc-4a23-bcd4-60e187acea99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059438734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3059438734
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.4106758309
Short name T417
Test name
Test status
Simulation time 32978161015 ps
CPU time 78.03 seconds
Started Jul 02 09:29:29 AM PDT 24
Finished Jul 02 09:30:47 AM PDT 24
Peak memory 183152 kb
Host smart-e447a9c2-4dfe-4ba1-ac9c-3c4944abc87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106758309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4106758309
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2900967234
Short name T170
Test name
Test status
Simulation time 155493083156 ps
CPU time 67.02 seconds
Started Jul 02 09:29:30 AM PDT 24
Finished Jul 02 09:30:37 AM PDT 24
Peak memory 191328 kb
Host smart-4c11a056-c572-41d3-8835-a11ead153abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900967234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2900967234
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.536750613
Short name T140
Test name
Test status
Simulation time 135469977132 ps
CPU time 428.14 seconds
Started Jul 02 09:29:30 AM PDT 24
Finished Jul 02 09:36:38 AM PDT 24
Peak memory 191348 kb
Host smart-cc432745-59f1-4675-be33-7fb370866dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536750613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.536750613
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.4172411332
Short name T352
Test name
Test status
Simulation time 10659655367 ps
CPU time 192.77 seconds
Started Jul 02 09:29:29 AM PDT 24
Finished Jul 02 09:32:42 AM PDT 24
Peak memory 183128 kb
Host smart-1aa2c4e2-6012-4871-a75e-36c35a354d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172411332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4172411332
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3082307608
Short name T163
Test name
Test status
Simulation time 133794369686 ps
CPU time 258.53 seconds
Started Jul 02 09:29:29 AM PDT 24
Finished Jul 02 09:33:48 AM PDT 24
Peak memory 191344 kb
Host smart-a1687ddc-395d-450b-af2a-0d438f1cd8fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082307608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3082307608
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2213154423
Short name T238
Test name
Test status
Simulation time 77099788796 ps
CPU time 395.1 seconds
Started Jul 02 09:29:36 AM PDT 24
Finished Jul 02 09:36:12 AM PDT 24
Peak memory 191300 kb
Host smart-50ab6e35-b335-4ec8-a90d-1cd474a203f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213154423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2213154423
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.483965450
Short name T285
Test name
Test status
Simulation time 245444326780 ps
CPU time 102.28 seconds
Started Jul 02 09:29:33 AM PDT 24
Finished Jul 02 09:31:16 AM PDT 24
Peak memory 191336 kb
Host smart-f40d516d-f9a4-4eeb-b740-8bfdbe2db206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483965450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.483965450
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.786650548
Short name T271
Test name
Test status
Simulation time 405919703953 ps
CPU time 194.33 seconds
Started Jul 02 09:29:34 AM PDT 24
Finished Jul 02 09:32:48 AM PDT 24
Peak memory 191336 kb
Host smart-f137581e-f76c-4ee1-aad7-2b43e90a9c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786650548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.786650548
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2441252811
Short name T226
Test name
Test status
Simulation time 683653404493 ps
CPU time 125.12 seconds
Started Jul 02 09:29:32 AM PDT 24
Finished Jul 02 09:31:38 AM PDT 24
Peak memory 191360 kb
Host smart-890a0c72-8929-46d4-8805-a40ff9d1508f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441252811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2441252811
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.948099481
Short name T70
Test name
Test status
Simulation time 115235468807 ps
CPU time 51.29 seconds
Started Jul 02 09:28:09 AM PDT 24
Finished Jul 02 09:29:01 AM PDT 24
Peak memory 183336 kb
Host smart-66ee18fb-2fe1-45f5-95a4-098954b1013a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948099481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.948099481
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3183033848
Short name T408
Test name
Test status
Simulation time 20280541428 ps
CPU time 26.16 seconds
Started Jul 02 09:28:05 AM PDT 24
Finished Jul 02 09:28:32 AM PDT 24
Peak memory 183144 kb
Host smart-ba73a768-9197-48b6-96ac-2a9862e5a592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183033848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3183033848
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4240035842
Short name T1
Test name
Test status
Simulation time 34230049418 ps
CPU time 22.46 seconds
Started Jul 02 09:28:03 AM PDT 24
Finished Jul 02 09:28:26 AM PDT 24
Peak memory 183092 kb
Host smart-fbb4e1db-57f8-4307-994d-15d3b0062ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240035842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4240035842
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3039428548
Short name T47
Test name
Test status
Simulation time 719639819359 ps
CPU time 1354.15 seconds
Started Jul 02 09:28:06 AM PDT 24
Finished Jul 02 09:50:41 AM PDT 24
Peak memory 183196 kb
Host smart-60c835aa-e819-40c1-ac80-37091f3e9237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039428548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3039428548
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3803019144
Short name T121
Test name
Test status
Simulation time 5606596485 ps
CPU time 5.01 seconds
Started Jul 02 09:29:36 AM PDT 24
Finished Jul 02 09:29:42 AM PDT 24
Peak memory 183144 kb
Host smart-df61b621-5a80-4efc-bf18-bf151c849b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803019144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3803019144
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1394850756
Short name T146
Test name
Test status
Simulation time 1003033368386 ps
CPU time 228.03 seconds
Started Jul 02 09:29:33 AM PDT 24
Finished Jul 02 09:33:21 AM PDT 24
Peak memory 191360 kb
Host smart-35da4485-6fbe-4e9c-a587-5919c8a7ab97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394850756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1394850756
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2561418446
Short name T319
Test name
Test status
Simulation time 93777711338 ps
CPU time 40.13 seconds
Started Jul 02 09:29:32 AM PDT 24
Finished Jul 02 09:30:12 AM PDT 24
Peak memory 183132 kb
Host smart-35d0dab0-2fee-4478-9949-a1673f715170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561418446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2561418446
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1781971067
Short name T278
Test name
Test status
Simulation time 98030453547 ps
CPU time 185.23 seconds
Started Jul 02 09:29:35 AM PDT 24
Finished Jul 02 09:32:41 AM PDT 24
Peak memory 191356 kb
Host smart-345f2158-f38e-4a6b-a484-23726d670eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781971067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1781971067
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3435314901
Short name T401
Test name
Test status
Simulation time 326998205310 ps
CPU time 99.83 seconds
Started Jul 02 09:29:36 AM PDT 24
Finished Jul 02 09:31:16 AM PDT 24
Peak memory 183108 kb
Host smart-e140afa1-4ae3-438d-b382-ce185dfd4019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435314901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3435314901
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4165698794
Short name T24
Test name
Test status
Simulation time 88281219781 ps
CPU time 148.01 seconds
Started Jul 02 09:29:35 AM PDT 24
Finished Jul 02 09:32:03 AM PDT 24
Peak memory 191316 kb
Host smart-cbc951e3-9eea-41f5-be9a-519e5088af46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165698794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4165698794
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.385715428
Short name T403
Test name
Test status
Simulation time 1366983804 ps
CPU time 1.81 seconds
Started Jul 02 09:29:36 AM PDT 24
Finished Jul 02 09:29:38 AM PDT 24
Peak memory 183112 kb
Host smart-45434e50-3cbb-4e5b-9473-ba8051b147af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385715428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.385715428
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.472688063
Short name T396
Test name
Test status
Simulation time 42606548577 ps
CPU time 64.82 seconds
Started Jul 02 09:29:38 AM PDT 24
Finished Jul 02 09:30:43 AM PDT 24
Peak memory 183112 kb
Host smart-bf3d0473-cf0b-462f-a4fe-0042d6368c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472688063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.472688063
Directory /workspace/99.rv_timer_random/latest
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