Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1395530	0	0
cfg0_rd_A	2147483647	4265	0	0
compare_lower0_0_rd_A	2147483647	3981	0	0
compare_upper0_0_rd_A	2147483647	3867	0	0
ctrl_rd_A	2147483647	4017	0	0
intr_enable0_rd_A	2147483647	4871	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1395530	0	0
T9	847926	178685	0	0
T10	933033	0	0	0
T11	157321	0	0	0
T12	226765	0	0	0
T13	0	52855	0	0
T14	0	128242	0	0
T34	255162	0	0	0
T35	365507	0	0	0
T36	0	106269	0	0
T37	0	38187	0	0
T38	0	42790	0	0
T39	0	177348	0	0
T40	0	90182	0	0
T41	0	442603	0	0
T42	0	27701	0	0
T43	158533	0	0	0
T44	483461	0	0	0
T45	425037	0	0	0
T46	226951	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4265	0	0
T30	0	47	0	0
T32	0	36	0	0
T36	601808	1294	0	0
T38	0	221	0	0
T42	0	270	0	0
T47	0	2	0	0
T48	0	26	0	0
T49	0	55	0	0
T50	0	125	0	0
T51	0	13	0	0
T52	206752	0	0	0
T53	968856	0	0	0
T54	737267	0	0	0
T55	105578	0	0	0
T56	146667	0	0	0
T57	447218	0	0	0
T58	103488	0	0	0
T59	970769	0	0	0
T60	713311	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3981	0	0
T30	0	49	0	0
T32	0	26	0	0
T36	601808	1274	0	0
T38	0	220	0	0
T42	0	324	0	0
T47	0	4	0	0
T48	0	23	0	0
T49	0	25	0	0
T50	0	79	0	0
T51	0	6	0	0
T52	206752	0	0	0
T53	968856	0	0	0
T54	737267	0	0	0
T55	105578	0	0	0
T56	146667	0	0	0
T57	447218	0	0	0
T58	103488	0	0	0
T59	970769	0	0	0
T60	713311	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3867	0	0
T30	0	47	0	0
T32	0	58	0	0
T36	601808	1039	0	0
T38	0	182	0	0
T42	0	305	0	0
T47	0	9	0	0
T48	0	43	0	0
T49	0	72	0	0
T50	0	76	0	0
T52	206752	0	0	0
T53	968856	0	0	0
T54	737267	0	0	0
T55	105578	0	0	0
T56	146667	0	0	0
T57	447218	0	0	0
T58	103488	0	0	0
T59	970769	0	0	0
T60	713311	0	0	0
T61	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4017	0	0
T30	0	44	0	0
T32	0	21	0	0
T36	601808	1132	0	0
T38	0	236	0	0
T42	0	241	0	0
T47	0	2	0	0
T48	0	20	0	0
T49	0	84	0	0
T50	0	88	0	0
T51	0	4	0	0
T52	206752	0	0	0
T53	968856	0	0	0
T54	737267	0	0	0
T55	105578	0	0	0
T56	146667	0	0	0
T57	447218	0	0	0
T58	103488	0	0	0
T59	970769	0	0	0
T60	713311	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4871	0	0
T25	456479	113	0	0
T26	401834	25	0	0
T27	444315	0	0	0
T28	43459	22	0	0
T36	0	1285	0	0
T38	0	240	0	0
T62	0	9	0	0
T63	0	52	0	0
T64	0	29	0	0
T65	0	36	0	0
T66	0	152	0	0
T67	463465	0	0	0
T68	164309	0	0	0
T69	453337	0	0	0
T70	127036	0	0	0
T71	476811	0	0	0
T72	7426	0	0	0