Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64574103	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	65101210	1		T1	2998		T2	186962		T3	24627

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	129225167	1		T1	5975		T2	375526		T3	49183
values[0x0]	215441	1		T1	7		T2	21		T3	14
values[0x1]	234705	1		T1	12		T2	27		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51589508	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	78085805	1		T1	3574		T2	224837		T3	29610

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	346799	1		T2	1450		T3	189		T4	45
valid_sources[0x01]	347323	1		T2	1685		T3	187		T4	68
valid_sources[0x02]	349318	1		T2	1407		T3	209		T4	41
valid_sources[0x03]	345113	1		T2	1726		T3	211		T4	52
valid_sources[0x04]	813129	1		T2	1751		T3	210		T4	45
valid_sources[0x05]	347990	1		T2	1672		T3	180		T4	49
valid_sources[0x06]	441155	1		T2	1578		T3	194		T4	48
valid_sources[0x07]	347402	1		T2	1704		T3	195		T4	42
valid_sources[0x08]	395587	1		T2	1185		T3	196		T4	35
valid_sources[0x09]	343770	1		T2	1668		T3	209		T4	55
valid_sources[0x0a]	351796	1		T2	1539		T3	206		T4	44
valid_sources[0x0b]	361383	1		T2	1463		T3	207		T4	45
valid_sources[0x0c]	2848380	1		T2	1470		T3	209		T4	69
valid_sources[0x0d]	348607	1		T2	1525		T3	210		T4	52
valid_sources[0x0e]	350832	1		T2	1373		T3	171		T4	50
valid_sources[0x0f]	344737	1		T2	1279		T3	187		T4	57
valid_sources[0x10]	346973	1		T2	1195		T3	224		T4	43
valid_sources[0x11]	346823	1		T2	1689		T3	184		T4	43
valid_sources[0x12]	348833	1		T2	1630		T3	178		T4	66
valid_sources[0x13]	423728	1		T2	1748		T3	204		T4	48
valid_sources[0x14]	348825	1		T2	1632		T3	210		T4	44
valid_sources[0x15]	2914524	1		T2	1444		T3	185		T4	52
valid_sources[0x16]	345080	1		T2	1646		T3	188		T4	46
valid_sources[0x17]	346562	1		T2	1383		T3	165		T4	39
valid_sources[0x18]	347882	1		T2	1586		T3	215		T4	62
valid_sources[0x19]	2565574	1		T2	1395		T3	191		T4	59
valid_sources[0x1a]	343751	1		T2	1763		T3	209		T4	47
valid_sources[0x1b]	346518	1		T2	1712		T3	215		T4	51
valid_sources[0x1c]	2146121	1		T2	1285		T3	204		T4	60
valid_sources[0x1d]	346006	1		T2	1608		T3	183		T4	27
valid_sources[0x1e]	346840	1		T2	1479		T3	188		T4	47
valid_sources[0x1f]	347310	1		T2	1353		T3	207		T4	50
valid_sources[0x20]	346890	1		T2	1402		T3	200		T4	51
valid_sources[0x21]	344676	1		T2	1435		T3	186		T4	50
valid_sources[0x22]	348712	1		T2	1570		T3	197		T4	46
valid_sources[0x23]	347011	1		T2	1567		T3	184		T4	52
valid_sources[0x24]	349185	1		T2	1408		T3	189		T4	44
valid_sources[0x25]	351189	1		T2	1375		T3	204		T4	48
valid_sources[0x26]	347541	1		T2	1486		T3	196		T4	36
valid_sources[0x27]	346615	1		T2	1556		T3	171		T4	38
valid_sources[0x28]	3431810	1		T2	1210		T3	220		T4	64
valid_sources[0x29]	720962	1		T2	1608		T3	183		T4	44
valid_sources[0x2a]	1206086	1		T2	1349		T3	193		T4	51
valid_sources[0x2b]	349372	1		T2	1583		T3	195		T4	55
valid_sources[0x2c]	382664	1		T2	1569		T3	191		T4	62
valid_sources[0x2d]	347391	1		T2	1541		T3	198		T4	57
valid_sources[0x2e]	345214	1		T2	1076		T3	204		T4	55
valid_sources[0x2f]	347943	1		T2	1608		T3	218		T4	50
valid_sources[0x30]	346608	1		T2	1367		T3	185		T4	65
valid_sources[0x31]	3529509	1		T2	1384		T3	178		T4	47
valid_sources[0x32]	352955	1		T2	1699		T3	206		T4	38
valid_sources[0x33]	348315	1		T2	1483		T3	193		T4	47
valid_sources[0x34]	344193	1		T2	1323		T3	184		T4	51
valid_sources[0x35]	1021352	1		T2	1324		T3	207		T4	48
valid_sources[0x36]	349086	1		T2	1311		T3	196		T4	60
valid_sources[0x37]	348760	1		T2	1538		T3	210		T4	63
valid_sources[0x38]	348115	1		T2	1534		T3	217		T4	31
valid_sources[0x39]	347565	1		T2	1513		T3	190		T4	52
valid_sources[0x3a]	347546	1		T2	1403		T3	202		T4	56
valid_sources[0x3b]	419561	1		T2	1477		T3	223		T4	41
valid_sources[0x3c]	347176	1		T2	1600		T3	217		T4	58
valid_sources[0x3d]	349322	1		T2	1226		T3	183		T4	42
valid_sources[0x3e]	349068	1		T2	1766		T3	186		T4	48
valid_sources[0x3f]	350836	1		T2	1729		T3	204		T4	51
valid_sources[0x40]	348342	1		T2	1530		T3	202		T4	51
valid_sources[0x41]	348147	1		T2	1415		T3	176		T4	45
valid_sources[0x42]	347143	1		T2	1463		T3	193		T4	61
valid_sources[0x43]	346193	1		T2	1516		T3	215		T4	47
valid_sources[0x44]	345331	1		T2	1455		T3	200		T4	45
valid_sources[0x45]	346582	1		T2	1454		T3	194		T4	42
valid_sources[0x46]	566763	1		T2	1382		T3	184		T4	60
valid_sources[0x47]	345483	1		T2	1781		T3	176		T4	51
valid_sources[0x48]	346538	1		T2	1801		T3	196		T4	48
valid_sources[0x49]	349929	1		T2	1510		T3	193		T4	57
valid_sources[0x4a]	347305	1		T2	1646		T3	185		T4	43
valid_sources[0x4b]	344912	1		T2	1467		T3	216		T4	52
valid_sources[0x4c]	351346	1		T2	1527		T3	171		T4	47
valid_sources[0x4d]	351012	1		T2	1254		T3	185		T4	68
valid_sources[0x4e]	345861	1		T2	1273		T3	222		T4	48
valid_sources[0x4f]	365463	1		T2	1552		T3	204		T4	59
valid_sources[0x50]	349332	1		T2	1324		T3	188		T4	50
valid_sources[0x51]	346400	1		T2	1560		T3	202		T4	56
valid_sources[0x52]	347404	1		T2	1653		T3	180		T4	52
valid_sources[0x53]	348885	1		T2	1311		T3	179		T4	37
valid_sources[0x54]	802360	1		T2	1651		T3	205		T4	57
valid_sources[0x55]	349867	1		T2	1763		T3	197		T4	66
valid_sources[0x56]	349607	1		T2	1627		T3	185		T4	62
valid_sources[0x57]	348986	1		T2	1745		T3	174		T4	54
valid_sources[0x58]	349731	1		T2	1443		T3	196		T4	43
valid_sources[0x59]	1229433	1		T2	1320		T3	201		T4	39
valid_sources[0x5a]	365063	1		T2	1391		T3	194		T4	54
valid_sources[0x5b]	347849	1		T2	1221		T3	217		T4	56
valid_sources[0x5c]	766240	1		T2	1522		T3	202		T4	40
valid_sources[0x5d]	346679	1		T2	1497		T3	189		T4	51
valid_sources[0x5e]	349605	1		T2	1368		T3	172		T4	44
valid_sources[0x5f]	622433	1		T2	1558		T3	162		T4	40
valid_sources[0x60]	345004	1		T2	1412		T3	172		T4	57
valid_sources[0x61]	348396	1		T2	1358		T3	209		T4	51
valid_sources[0x62]	351948	1		T2	1294		T3	209		T4	64
valid_sources[0x63]	347159	1		T2	1215		T3	183		T4	36
valid_sources[0x64]	706419	1		T2	1247		T3	173		T4	48
valid_sources[0x65]	386880	1		T2	1646		T3	223		T4	61
valid_sources[0x66]	345990	1		T2	1373		T3	201		T4	42
valid_sources[0x67]	349598	1		T2	1537		T3	216		T4	51
valid_sources[0x68]	347160	1		T2	1516		T3	166		T4	44
valid_sources[0x69]	349087	1		T2	1385		T3	201		T4	55
valid_sources[0x6a]	348583	1		T2	1632		T3	196		T4	58
valid_sources[0x6b]	349764	1		T2	1526		T3	184		T4	57
valid_sources[0x6c]	357766	1		T1	5994		T2	1266		T3	200
valid_sources[0x6d]	346299	1		T2	1513		T3	172		T4	62
valid_sources[0x6e]	348065	1		T2	1394		T3	183		T4	54
valid_sources[0x6f]	402104	1		T2	1388		T3	178		T4	48
valid_sources[0x70]	350136	1		T2	1372		T3	201		T4	44
valid_sources[0x71]	371450	1		T2	1858		T3	175		T4	42
valid_sources[0x72]	349803	1		T2	1675		T3	194		T4	62
valid_sources[0x73]	347469	1		T2	1553		T3	178		T4	68
valid_sources[0x74]	344901	1		T2	1357		T3	201		T4	64
valid_sources[0x75]	378607	1		T2	1369		T3	214		T4	53
valid_sources[0x76]	346259	1		T2	1327		T3	166		T4	65
valid_sources[0x77]	1818463	1		T2	1639		T3	213		T4	39
valid_sources[0x78]	546067	1		T2	1613		T3	190		T4	49
valid_sources[0x79]	346274	1		T2	1238		T3	198		T4	38
valid_sources[0x7a]	349278	1		T2	1619		T3	191		T4	50
valid_sources[0x7b]	349007	1		T2	1442		T3	192		T4	53
valid_sources[0x7c]	345902	1		T2	1510		T3	203		T4	58
valid_sources[0x7d]	348578	1		T2	1752		T3	219		T4	49
valid_sources[0x7e]	346690	1		T2	1517		T3	183		T4	43
valid_sources[0x7f]	348188	1		T2	1560		T3	181		T4	52
valid_sources[0x80]	735674	1		T2	1586		T3	196		T4	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64687501

1

T1

2984

T2

186926

T3

24608

values[0x0]

all_enables

biggest_size

208367

1

T1

4

T2

16

T3

7

values[0x1]

all_enables

biggest_size

205342

1

T1

10

T2

20

T3

12