Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	678764	0	0
cfg0_rd_A	2147483647	3353	0	0
compare_lower0_0_rd_A	2147483647	3082	0	0
compare_upper0_0_rd_A	2147483647	2968	0	0
ctrl_rd_A	2147483647	2857	0	0
intr_enable0_rd_A	2147483647	4247	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	678764	0	0
T13	208098	84259	0	0
T14	0	121440	0	0
T15	0	304702	0	0
T30	0	15	0	0
T31	0	9	0	0
T37	0	21443	0	0
T38	0	133845	0	0
T39	0	176	0	0
T40	0	263	0	0
T41	0	619	0	0
T42	120500	0	0	0
T43	301086	0	0	0
T44	837810	0	0	0
T45	439898	0	0	0
T46	522117	0	0	0
T47	793983	0	0	0
T48	286128	0	0	0
T49	891120	0	0	0
T50	948531	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3353	0	0
T14	478563	1105	0	0
T30	0	177	0	0
T34	0	11	0	0
T35	0	56	0	0
T51	0	31	0	0
T52	0	18	0	0
T53	0	13	0	0
T54	0	17	0	0
T55	0	20	0	0
T56	0	6	0	0
T57	658946	0	0	0
T58	189321	0	0	0
T59	998227	0	0	0
T60	524115	0	0	0
T61	107543	0	0	0
T62	501573	0	0	0
T63	171130	0	0	0
T64	335087	0	0	0
T65	440859	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3082	0	0
T14	478563	1303	0	0
T30	0	111	0	0
T34	0	69	0	0
T35	0	40	0	0
T51	0	52	0	0
T52	0	10	0	0
T53	0	13	0	0
T54	0	3	0	0
T55	0	18	0	0
T56	0	9	0	0
T57	658946	0	0	0
T58	189321	0	0	0
T59	998227	0	0	0
T60	524115	0	0	0
T61	107543	0	0	0
T62	501573	0	0	0
T63	171130	0	0	0
T64	335087	0	0	0
T65	440859	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2968	0	0
T14	478563	1221	0	0
T30	0	130	0	0
T34	0	14	0	0
T35	0	84	0	0
T51	0	19	0	0
T52	0	12	0	0
T53	0	10	0	0
T54	0	15	0	0
T55	0	5	0	0
T56	0	3	0	0
T57	658946	0	0	0
T58	189321	0	0	0
T59	998227	0	0	0
T60	524115	0	0	0
T61	107543	0	0	0
T62	501573	0	0	0
T63	171130	0	0	0
T64	335087	0	0	0
T65	440859	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2857	0	0
T14	478563	1072	0	0
T30	0	144	0	0
T34	0	34	0	0
T35	0	31	0	0
T51	0	21	0	0
T52	0	12	0	0
T54	0	14	0	0
T55	0	9	0	0
T56	0	5	0	0
T57	658946	0	0	0
T58	189321	0	0	0
T59	998227	0	0	0
T60	524115	0	0	0
T61	107543	0	0	0
T62	501573	0	0	0
T63	171130	0	0	0
T64	335087	0	0	0
T65	440859	0	0	0
T66	0	73	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4247	0	0
T14	0	1819	0	0
T67	266548	67	0	0
T68	0	49	0	0
T69	0	69	0	0
T70	0	20	0	0
T71	0	17	0	0
T72	0	23	0	0
T73	0	24	0	0
T74	0	24	0	0
T75	0	113	0	0
T76	447738	0	0	0
T77	129425	0	0	0
T78	331212	0	0	0
T79	821196	0	0	0
T80	440542	0	0	0
T81	982666	0	0	0
T82	312902	0	0	0
T83	760044	0	0	0
T84	115222	0	0	0