Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	69730444	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	71208838	1		T1	8269		T2	108406		T3	3359

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	139666834	1		T1	16533		T2	216457		T3	6676
values[0x0]	603876	1		T1	14		T2	29		T3	13
values[0x1]	668572	1		T1	6		T2	28		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55689074	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	85250208	1		T1	9924		T2	130335		T3	4028

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	395327	1		T1	71		T5	2385		T10	675
valid_sources[0x01]	434931	1		T1	61		T5	2459		T6	2
valid_sources[0x02]	394658	1		T1	58		T5	2400		T6	2
valid_sources[0x03]	1103768	1		T1	63		T5	2446		T6	4
valid_sources[0x04]	396759	1		T1	65		T5	2504		T6	4
valid_sources[0x05]	475146	1		T1	66		T5	2359		T6	5
valid_sources[0x06]	397852	1		T1	71		T5	2406		T6	1
valid_sources[0x07]	390267	1		T1	47		T5	2402		T6	4
valid_sources[0x08]	395150	1		T1	81		T5	2366		T6	5
valid_sources[0x09]	400396	1		T1	84		T5	2455		T6	22
valid_sources[0x0a]	396355	1		T1	55		T5	2440		T6	8
valid_sources[0x0b]	403464	1		T1	55		T5	2347		T6	20
valid_sources[0x0c]	419184	1		T1	61		T5	2364		T6	30
valid_sources[0x0d]	402498	1		T1	55		T5	2518		T6	11
valid_sources[0x0e]	394308	1		T1	41		T5	2408		T6	4
valid_sources[0x0f]	393905	1		T1	75		T5	2356		T6	11
valid_sources[0x10]	519700	1		T1	94		T5	2331		T6	13
valid_sources[0x11]	436830	1		T1	85		T5	2397		T6	8
valid_sources[0x12]	392932	1		T1	62		T5	2478		T6	3
valid_sources[0x13]	881897	1		T1	67		T5	2330		T6	17
valid_sources[0x14]	394614	1		T1	67		T5	2401		T6	11
valid_sources[0x15]	394498	1		T1	73		T5	2495		T6	8
valid_sources[0x16]	394223	1		T1	48		T5	2395		T6	12
valid_sources[0x17]	389770	1		T1	62		T5	2491		T6	1
valid_sources[0x18]	390877	1		T1	73		T5	2466		T6	8
valid_sources[0x19]	392676	1		T1	67		T5	2376		T6	8
valid_sources[0x1a]	392940	1		T1	66		T5	2447		T6	16
valid_sources[0x1b]	390621	1		T1	49		T5	2308		T6	9
valid_sources[0x1c]	392067	1		T1	63		T5	2452		T6	17
valid_sources[0x1d]	419778	1		T1	53		T5	2321		T6	26
valid_sources[0x1e]	399548	1		T1	57		T5	2418		T6	2
valid_sources[0x1f]	391797	1		T1	56		T5	2371		T6	13
valid_sources[0x20]	2219791	1		T1	56		T5	2412		T6	27
valid_sources[0x21]	2196865	1		T1	68		T4	180015		T5	2395
valid_sources[0x22]	401675	1		T1	43		T5	2402		T6	2
valid_sources[0x23]	549831	1		T1	69		T5	2450		T6	14
valid_sources[0x24]	392021	1		T1	81		T5	2356		T6	14
valid_sources[0x25]	457791	1		T1	60		T5	2385		T6	11
valid_sources[0x26]	395079	1		T1	56		T5	2401		T6	2
valid_sources[0x27]	390285	1		T1	50		T5	2407		T6	7
valid_sources[0x28]	393855	1		T1	62		T5	2327		T6	5
valid_sources[0x29]	420432	1		T1	50		T5	2401		T6	9
valid_sources[0x2a]	398055	1		T1	71		T5	2421		T6	7
valid_sources[0x2b]	390572	1		T1	88		T5	2396		T10	549
valid_sources[0x2c]	713285	1		T1	66		T5	2453		T6	2
valid_sources[0x2d]	392061	1		T1	68		T5	2379		T6	12
valid_sources[0x2e]	394249	1		T1	83		T5	2447		T6	7
valid_sources[0x2f]	390704	1		T1	72		T5	2387		T6	1
valid_sources[0x30]	659227	1		T1	45		T5	2359		T6	16
valid_sources[0x31]	1195431	1		T1	68		T5	2351		T6	1
valid_sources[0x32]	1661511	1		T1	64		T5	2406		T6	1
valid_sources[0x33]	397316	1		T1	67		T5	2314		T10	478
valid_sources[0x34]	576462	1		T1	77		T5	2454		T6	18
valid_sources[0x35]	397822	1		T1	69		T5	2449		T10	648
valid_sources[0x36]	389831	1		T1	65		T5	2316		T6	10
valid_sources[0x37]	396263	1		T1	65		T5	2405		T6	8
valid_sources[0x38]	394127	1		T1	61		T5	2374		T6	4
valid_sources[0x39]	396160	1		T1	45		T5	2419		T6	4
valid_sources[0x3a]	434040	1		T1	57		T5	2433		T6	9
valid_sources[0x3b]	392967	1		T1	53		T5	2449		T6	15
valid_sources[0x3c]	399556	1		T1	49		T5	2405		T6	4
valid_sources[0x3d]	394226	1		T1	90		T5	2431		T6	8
valid_sources[0x3e]	396635	1		T1	69		T5	2441		T6	15
valid_sources[0x3f]	388650	1		T1	82		T5	2399		T6	13
valid_sources[0x40]	420522	1		T1	57		T5	2442		T6	21
valid_sources[0x41]	395183	1		T1	68		T5	2451		T6	11
valid_sources[0x42]	393665	1		T1	82		T5	2441		T6	1
valid_sources[0x43]	392888	1		T1	76		T5	2444		T6	19
valid_sources[0x44]	390650	1		T1	74		T5	2440		T6	13
valid_sources[0x45]	1379532	1		T1	62		T5	2384		T6	3
valid_sources[0x46]	391470	1		T1	69		T5	2391		T6	2
valid_sources[0x47]	989685	1		T1	75		T5	2378		T6	7
valid_sources[0x48]	1784686	1		T1	64		T5	2526		T6	2
valid_sources[0x49]	393106	1		T1	71		T5	2396		T6	7
valid_sources[0x4a]	396210	1		T1	55		T5	2347		T6	10
valid_sources[0x4b]	417951	1		T1	83		T5	2438		T6	12
valid_sources[0x4c]	395877	1		T1	68		T5	2401		T6	22
valid_sources[0x4d]	1938767	1		T1	67		T5	2446		T6	7
valid_sources[0x4e]	397173	1		T1	58		T5	2431		T6	7
valid_sources[0x4f]	393892	1		T1	68		T5	2376		T6	10
valid_sources[0x50]	393704	1		T1	55		T5	2385		T6	10
valid_sources[0x51]	408374	1		T1	69		T5	2366		T6	18
valid_sources[0x52]	395245	1		T1	62		T5	2376		T6	15
valid_sources[0x53]	395040	1		T1	68		T5	2362		T6	2
valid_sources[0x54]	398414	1		T1	62		T5	2314		T6	8
valid_sources[0x55]	388125	1		T1	43		T5	2486		T6	19
valid_sources[0x56]	449085	1		T1	49		T5	2391		T6	6
valid_sources[0x57]	396115	1		T1	67		T5	2370		T6	2
valid_sources[0x58]	396218	1		T1	53		T5	2375		T6	3
valid_sources[0x59]	387580	1		T1	89		T5	2355		T6	2
valid_sources[0x5a]	437876	1		T1	54		T5	2422		T6	1
valid_sources[0x5b]	394907	1		T1	73		T5	2439		T6	10
valid_sources[0x5c]	396376	1		T1	50		T5	2373		T6	5
valid_sources[0x5d]	546825	1		T1	56		T5	2390		T6	8
valid_sources[0x5e]	393699	1		T1	77		T5	2288		T6	3
valid_sources[0x5f]	402612	1		T1	55		T5	2372		T6	11
valid_sources[0x60]	408820	1		T1	65		T5	2336		T6	7
valid_sources[0x61]	431778	1		T1	66		T5	2428		T6	7
valid_sources[0x62]	394524	1		T1	57		T5	2399		T6	10
valid_sources[0x63]	412557	1		T1	71		T5	2456		T6	6
valid_sources[0x64]	650292	1		T1	72		T5	2317		T6	4
valid_sources[0x65]	398874	1		T1	82		T5	2447		T6	9
valid_sources[0x66]	394476	1		T1	64		T5	2450		T6	6
valid_sources[0x67]	1644377	1		T1	69		T5	2413		T6	9
valid_sources[0x68]	390175	1		T1	72		T5	2420		T6	1
valid_sources[0x69]	392678	1		T1	76		T5	2434		T6	4
valid_sources[0x6a]	398231	1		T1	75		T5	2438		T6	5
valid_sources[0x6b]	392520	1		T1	39		T5	2432		T6	2
valid_sources[0x6c]	393244	1		T1	65		T5	2416		T6	12
valid_sources[0x6d]	2493297	1		T1	63		T5	2453		T6	4
valid_sources[0x6e]	425213	1		T1	54		T5	2413		T6	14
valid_sources[0x6f]	397142	1		T1	73		T5	2495		T6	13
valid_sources[0x70]	784853	1		T1	62		T5	2509		T6	8
valid_sources[0x71]	391292	1		T1	44		T5	2323		T6	3
valid_sources[0x72]	396694	1		T1	66		T5	2366		T6	7
valid_sources[0x73]	393462	1		T1	68		T5	2423		T6	4
valid_sources[0x74]	392529	1		T1	60		T5	2424		T6	4
valid_sources[0x75]	393222	1		T1	51		T5	2344		T6	2
valid_sources[0x76]	391337	1		T1	56		T5	2403		T6	15
valid_sources[0x77]	424099	1		T1	88		T5	2382		T6	5
valid_sources[0x78]	390846	1		T1	61		T5	2360		T6	8
valid_sources[0x79]	946955	1		T1	66		T5	2357		T6	3
valid_sources[0x7a]	399745	1		T1	64		T3	6701		T5	2337
valid_sources[0x7b]	397649	1		T1	77		T5	2381		T6	6
valid_sources[0x7c]	391951	1		T1	71		T5	2393		T6	13
valid_sources[0x7d]	394458	1		T1	55		T5	2333		T6	10
valid_sources[0x7e]	857875	1		T1	75		T5	2472		T6	3
valid_sources[0x7f]	394573	1		T1	69		T5	2457		T6	11
valid_sources[0x80]	412034	1		T1	61		T5	2352		T6	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70025390

1

T1

8257

T2

108365

T3

3336

values[0x0]

all_enables

biggest_size

592296

1

T1

8

T2

23

T3

12

values[0x1]

all_enables

biggest_size

591152

1

T1

4

T2

18

T3

11