Unified Coverage Report :: Module :: rv_timer_csr_assert_fpv

Module : rv_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_timer_csr_assert_0/rv_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2086876	0	0
cfg0_rd_A	2147483647	4109	0	0
compare_lower0_0_rd_A	2147483647	4225	0	0
compare_upper0_0_rd_A	2147483647	4125	0	0
ctrl_rd_A	2147483647	4182	0	0
intr_enable0_rd_A	2147483647	4830	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2086876	0	0
T11	941834	285603	0	0
T12	557988	171245	0	0
T13	0	167439	0	0
T34	0	67350	0	0
T35	0	81538	0	0
T36	0	70794	0	0
T37	0	82059	0	0
T38	0	84073	0	0
T39	0	55980	0	0
T40	0	119137	0	0
T41	244194	0	0	0
T42	135553	0	0	0
T43	230027	0	0	0
T44	652715	0	0	0
T45	470760	0	0	0
T46	398176	0	0	0
T47	150192	0	0	0
T48	463781	0	0	0

cfg0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4109	0	0
T14	5792	0	0	0
T19	151026	0	0	0
T20	168225	0	0	0
T21	635781	0	0	0
T22	375869	0	0	0
T28	0	180	0	0
T36	268080	674	0	0
T38	0	379	0	0
T49	0	11	0	0
T50	0	15	0	0
T51	0	14	0	0
T52	0	66	0	0
T53	0	35	0	0
T54	0	45	0	0
T55	0	10	0	0
T56	493704	0	0	0
T57	672539	0	0	0
T58	613297	0	0	0
T59	179026	0	0	0

compare_lower0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4225	0	0
T14	5792	0	0	0
T19	151026	0	0	0
T20	168225	0	0	0
T21	635781	0	0	0
T22	375869	0	0	0
T28	0	108	0	0
T36	268080	798	0	0
T38	0	539	0	0
T49	0	23	0	0
T50	0	14	0	0
T51	0	10	0	0
T52	0	59	0	0
T53	0	32	0	0
T54	0	111	0	0
T55	0	22	0	0
T56	493704	0	0	0
T57	672539	0	0	0
T58	613297	0	0	0
T59	179026	0	0	0

compare_upper0_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4125	0	0
T14	5792	0	0	0
T19	151026	0	0	0
T20	168225	0	0	0
T21	635781	0	0	0
T22	375869	0	0	0
T28	0	106	0	0
T36	268080	731	0	0
T38	0	443	0	0
T49	0	36	0	0
T50	0	6	0	0
T51	0	7	0	0
T52	0	76	0	0
T53	0	7	0	0
T54	0	97	0	0
T55	0	38	0	0
T56	493704	0	0	0
T57	672539	0	0	0
T58	613297	0	0	0
T59	179026	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4182	0	0
T14	5792	0	0	0
T19	151026	0	0	0
T20	168225	0	0	0
T21	635781	0	0	0
T22	375869	0	0	0
T28	0	104	0	0
T36	268080	752	0	0
T38	0	434	0	0
T49	0	22	0	0
T50	0	3	0	0
T51	0	3	0	0
T52	0	59	0	0
T53	0	66	0	0
T54	0	66	0	0
T55	0	26	0	0
T56	493704	0	0	0
T57	672539	0	0	0
T58	613297	0	0	0
T59	179026	0	0	0

intr_enable0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4830	0	0
T8	276378	41	0	0
T9	469186	0	0	0
T10	107672	0	0	0
T36	0	920	0	0
T38	0	490	0	0
T49	0	26	0	0
T60	0	13	0	0
T61	0	43	0	0
T62	0	32	0	0
T63	0	60	0	0
T64	0	32	0	0
T65	0	22	0	0
T66	820788	0	0	0
T67	155290	0	0	0
T68	538296	0	0	0
T69	947312	0	0	0
T70	11871	0	0	0
T71	114107	0	0	0
T72	104297	0	0	0